2016-03-28 16:24:37 +01:00
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/*************************************************************************************
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Grid physics library, www.github.com/paboyle/Grid
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Source file: ./lib/simd/Avx512Asm.h
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Copyright (C) 2015
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Author: paboyle <paboyle@ph.ed.ac.uk>
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This program is free software; you can redistribute it and/or modify
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it under the terms of the GNU General Public License as published by
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the Free Software Foundation; either version 2 of the License, or
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(at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License along
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with this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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See the full license in the file "LICENSE" in the top level distribution directory
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*************************************************************************************/
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/* END LEGAL */
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#ifndef GRID_ASM_AV512_ADDSUB_H
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#define GRID_ASM_AV512_ADDSUB_H
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////////////////////////////////////////////////////////////////
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// Building blocks for SU3 x 2spinor
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// Load columns of U
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// 18 U DUP's rr/ii
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// 6 Chi shuffles ir,ri
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// 6muls, 30 fmaddsubs
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////////////////////////////////////////////////////////////////
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2016-03-29 00:55:22 +01:00
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#define MULT_ADDSUB_2SPIN(ptr) \
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2016-03-28 16:24:37 +01:00
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LOAD64(%r8,ptr) \
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__asm__ ( \
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VMOVIDUPf(0,%r8,Z0 ) \
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VMOVIDUPf(3,%r8,Z1 )\
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VMOVIDUPf(6,%r8,Z2 )\
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VSHUFf(Chi_00,T1) \
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VSHUFf(Chi_10,T2) \
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\
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VMULf(Z0,T1,UChi_00) VMOVRDUPf(0,%r8,Z3 ) \
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VMULf(Z0,T2,UChi_10) VMOVRDUPf(3,%r8,Z4 ) \
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VMULf(Z1,T1,UChi_01) VMOVRDUPf(6,%r8,Z5 ) \
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VMULf(Z1,T2,UChi_11) VMOVIDUPf(1,%r8,Z0 ) \
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VMULf(Z2,T1,UChi_02) VMOVIDUPf(4,%r8,Z1 ) \
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VMULf(Z2,T2,UChi_12) VMOVIDUPf(7,%r8,Z2 ) \
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\
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VMADDSUBf(Z3,Chi_00,UChi_00) VSHUFf(Chi_01,T1) \
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VMADDSUBf(Z3,Chi_10,UChi_10) VSHUFf(Chi_11,T2) \
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VMADDSUBf(Z4,Chi_00,UChi_01) VMOVRDUPf(1,%r8,Z3 ) \
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VMADDSUBf(Z4,Chi_10,UChi_11)\
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VMADDSUBf(Z5,Chi_00,UChi_02) VMOVRDUPf(4,%r8,Z4 ) \
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VMADDSUBf(Z5,Chi_10,UChi_12)\
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\
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VMADDSUBf(Z0,T1,UChi_00) VMOVRDUPf(7,%r8,Z5 ) \
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VMADDSUBf(Z0,T2,UChi_10)\
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VMADDSUBf(Z1,T1,UChi_01) VMOVIDUPf(2,%r8,Z0 ) \
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VMADDSUBf(Z1,T2,UChi_11)\
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VMADDSUBf(Z2,T1,UChi_02) VMOVIDUPf(5,%r8,Z1 ) \
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VMADDSUBf(Z2,T2,UChi_12) VMOVIDUPf(8,%r8,Z2 ) \
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\
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VMADDSUBf(Z3,Chi_01,UChi_00) VSHUFf(Chi_02,T1) \
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VMADDSUBf(Z3,Chi_11,UChi_10) VSHUFf(Chi_12,T2) \
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VMADDSUBf(Z4,Chi_01,UChi_01) VMOVRDUPf(2,%r8,Z3 ) \
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VMADDSUBf(Z4,Chi_11,UChi_11)\
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VMADDSUBf(Z5,Chi_01,UChi_02) VMOVRDUPf(5,%r8,Z4 ) \
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VMADDSUBf(Z5,Chi_11,UChi_12)\
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\
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VMADDSUBf(Z0,T1,UChi_00) VMOVRDUPf(8,%r8,Z5 ) \
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VMADDSUBf(Z0,T2,UChi_10)\
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VMADDSUBf(Z1,T1,UChi_01)\
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VMADDSUBf(Z1,T2,UChi_11)\
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VMADDSUBf(Z2,T1,UChi_02)\
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VMADDSUBf(Z2,T2,UChi_12)\
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\
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VMADDSUBf(Z3,Chi_02,UChi_00)\
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VMADDSUBf(Z3,Chi_12,UChi_10)\
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VMADDSUBf(Z4,Chi_02,UChi_01)\
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VMADDSUBf(Z4,Chi_12,UChi_11)\
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VMADDSUBf(Z5,Chi_02,UChi_02)\
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VMADDSUBf(Z5,Chi_12,UChi_12)\
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);
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#endif
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