5 Commits

Author	SHA1	Message	Date
neo	744ac33e8b	Experimental support for ARM	2015-06-09 15:46:21 +09:00
Azusa Yamaguchi	8f9627520b	merge to the head	2015-06-05 10:15:31 +01:00
neo	7fb3221d47	Partial implementation of the vector types SIMD ... Implementing SSE4 now A systematic series of tests must be written.	2015-05-19 17:21:17 +09:00
neo	639fd05239	Added check of mpfr and gmp at configure time ... It generates automatically the linker flags or complains if not found.	2015-05-19 13:54:55 +09:00
neo	6d2accba7b	Corrected some compilation errors (zolotarev.h) and SSE4 vsplat and conj to make cshift test pass.	2015-05-18 16:48:14 +09:00