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Author SHA1 Message Date
Peter Boyle
7533f66b54 Fix compile 2021-05-06 23:24:39 +02:00
Peter Boyle
805cde5899 Fix compile 2021-05-06 23:24:19 +02:00
Peter Boyle
a0534e03f9 Augmented test 2021-05-06 23:23:57 +02:00
Peter Boyle
ebba195e0d Code prettier 2021-05-06 23:23:30 +02:00
Peter Boyle
3b433fe6fb Better force logging 2021-05-06 23:22:09 +02:00
Peter Boyle
07d1030660 Schur solver for Mdag 2021-05-06 23:21:15 +02:00
Peter Boyle
f8d7d23893 4D pseudofermion options 2021-05-06 23:19:53 +02:00
Peter Boyle
cdeb718229 4D pseudo fermion, with Schur red black solvers 2021-05-06 23:15:16 +02:00
Peter Boyle
cb28568198 Tuning integrator 2021-05-06 23:12:57 +02:00
Peter Boyle
45440da79d Tuning integrator 2021-05-06 23:12:34 +02:00
Peter Boyle
6fe8533414 Mdagger solve support 2021-05-06 23:10:36 +02:00
Peter Boyle
21165ed489 Better logging and moving momentumfilter 2021-04-10 01:08:23 +02:00
Peter Boyle
09288d633c 4D pseudofermoin 2021-04-10 01:06:52 +02:00
Peter Boyle
fe00c96435 4D Pseudofermion support 2021-04-10 01:06:11 +02:00
Peter Boyle
0765f30308 4D pseudo fermion support 2021-04-10 01:05:42 +02:00
Peter Boyle
a6326b664e Move momenutm filter to earlier in the include sequence so it can be used by DDHMC 2021-04-10 01:04:16 +02:00
Peter Boyle
ccd30e1485 4D pseudofermion in Cayley action 2021-04-10 01:03:01 +02:00
Peter Boyle
3060887a37 Merge branch 'develop' into feature/ddhmc 2021-03-31 19:48:31 +02:00
Peter Boyle
b53059344e Better test on non-unit gauge 2021-03-31 13:45:06 -04:00
Peter Boyle
aaf5ebf345 Small hack 2021-03-31 19:32:57 +02:00
Peter Boyle
48edb8f72e HMC prep for DDHMC 2021-03-31 19:31:46 +02:00
Peter Boyle
a7fb25adf6 Make Cshift fields static to avoid repeated reallocaate overhead 2021-03-29 21:44:14 +02:00
Peter Boyle
e947992957 Improved force terms 2021-03-29 20:04:06 +02:00
Peter Boyle
bb89a82a07 Staggered coalseced read 2021-03-29 20:01:15 +02:00
Peter Boyle
8bdadbadac Cold start 2021-03-18 15:41:14 -04:00
Peter Boyle
15c50a7442 Explicit instantiate the template function 2021-03-18 15:40:42 -04:00
Peter Boyle
49b0af2c95 Update of tests to compile with the sRNG addition. 
Audited the code conventions (again) with the CPS momentum denominator
and added anti periodic in time to the Test_mobius_force.cc and
tested the Test_dwf_gpforce.

Promoted thesee to test full HMC hamiltonian, tr P^2/2 + phidag MdagM phi

with the same pdot and Udot as audited in the Integrator.h etc...

With full comments and sources for factors.
 2021-03-18 09:10:02 -04:00
Peter Boyle
9c2b37218a sRNG parameter added 2021-03-18 06:24:11 -04:00
Peter Boyle
3c67d626ba Merge branch 'develop' of https://github.com/paboyle/Grid into develop 2021-03-12 15:36:55 +01:00
Peter Boyle
51f506553c Read out the local ID once, and store 2021-03-12 15:33:04 +01:00
Peter Boyle
226be84937 Merge branch 'develop' of https://github.com/paboyle/Grid into develop 2021-03-12 09:31:50 -05:00
Peter Boyle
001814b442 updated to do list. Start adding DDHMC work items 2021-03-12 09:31:17 -05:00
Peter Boyle
db3ac67506 Update thread issue 2021-03-12 14:55:07 +01:00
Peter Boyle
da91a884ef NVCC versions found buggy added as guard 2021-03-11 23:54:53 +01:00
Peter Boyle
a71e6755e3 Merge branch 'develop' of https://github.com/paboyle/Grid into develop 2021-03-11 22:43:06 +01:00
Peter Boyle
cd5891eecd Test that fails on Cuda 11.0 2021-03-11 22:34:28 +01:00
Peter Boyle
5bb7336f27
Merge pull request #347 from pjgeorg/fix-autotools-avx512 
Fix inconsistent SIMD option AVX512

Thanks
 2021-03-11 16:29:07 -05:00
Peter Boyle
ce1fc1f48a Possible fallback plan for Fionn's compiler bbug in nvcc 2021-03-11 22:20:53 +01:00
Peter Georg
82402c6a7c Add simd option SKL for ICC 2021-03-11 13:08:40 +01:00
Peter Georg
d9c4afe5b7 Fix inconsistent configure option AVX512 
Before this change AVX512 enabled different instruction sets depending
on the compiler:

For Intel C++ Compiler Classic (ICC):
    AVX512F, AVX512CD, AVX512DQ, AVX512BW, AVX512VL
    i.e. Intel Xeon Skylake and newer

For Intel ICX, gcc, clang:
    AVX512F, AVX512CD, AVX512ER, AVX512PF
    i.e. Intel Xeon Phi x200/x205 (KNL/KNM)

With this commit AVX512 now only enables the common instruction sets
supported by all CPUs supporting any AVX-512 instructions set:
AVX512F and AVX512CD (called COMMON-AVX512 by icc)
 2021-03-11 12:58:49 +01:00
Peter Boyle
f786ff8d69 Extend test from Fionn, fails on A100 apparently 2021-03-10 14:32:06 -05:00
u61464
a651caed5f Merge branch 'develop' of https://github.com/paboyle/Grid into develop 2021-03-10 06:23:51 -08:00
u61464
0e21adb3f6 Gives 200GF/s on SyCL/DG1 8^4, doesn't uglify develop for other platforms too badly. 
Easy to revert to clean more C++ stylistic code. Theres a SYCL_HACK macro I will clean up later once dpcpp
evolves a central nervous systems.
 2021-03-10 05:40:51 -08:00
Peter Boyle
58bf9b9e6d Clean up test 2021-03-10 02:45:22 +01:00
Peter Boyle
2146eebb65 Merge branch 'develop' of https://github.com/paboyle/Grid into develop 2021-03-09 04:31:46 +01:00
Peter Boyle
6a429ee6d3 2d loop hits Nvidia 16bit limit on large local vols 2021-03-09 04:31:10 +01:00
Peter Boyle
4d1ea15c79 More verbosity. The 16bit limit on Grid.y, Grid.z is annoying 2021-03-09 04:29:37 +01:00
Peter Boyle
a76cb005e0
Update Tensor_exp.h 2021-03-08 13:37:57 -05:00
Peter Boyle
a9604367c1
Merge pull request #336 from lehner/feature/gpt 
Make ShmDims configurable; adjust GRID_MAX_SIMD to allow for 128 byte width on GPUs
 2021-03-05 13:17:19 -05:00
Peter Boyle
d7065023cc
Merge pull request #332 from mmphys/feature/mres_schur 
Optional changes to Test_cayley_mres e.g. Schur solver
 2021-03-05 12:47:07 -05:00