Antonin Portelli portelli
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  • Joined on 2017-10-25
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portelli pushed to main at portelli/lattice-benchmarks 2023-12-20 15:06:42 +00:00
ba00493c7d Merge pull request 'fix incompatibility with latest Grid' (#5) from simon.buerger/lattice-benchmarks:main into main
6ea093fc80 fix incompatibility with latest Grid
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portelli synced commits to refs/pull/379/merge at portelli/Grid from mirror 2023-12-12 13:11:44 +00:00
e5bc679fef Merge 32e6d58356 into f48298ad4e
f48298ad4e Bug fix
645e47c1ba Config for Ampere Altra ARM
d1d9827263 Integrator logging update
14643c0aab SDCC benchmarking scripts for A100 nodes and IceLake nodes (AVX512)
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portelli synced commits to develop at portelli/Grid from mirror 2023-12-12 05:01:44 +00:00
f48298ad4e Bug fix
portelli synced commits to develop at portelli/Grid from mirror 2023-12-09 03:31:44 +00:00
645e47c1ba Config for Ampere Altra ARM
portelli synced commits to develop at portelli/Grid from mirror 2023-12-08 19:21:45 +00:00
d1d9827263 Integrator logging update
portelli synced commits to develop at portelli/Grid from mirror 2023-12-05 01:31:44 +00:00
14643c0aab SDCC benchmarking scripts for A100 nodes and IceLake nodes (AVX512)
portelli synced commits to develop at portelli/Grid from mirror 2023-11-30 23:31:44 +00:00
b77a9b8947 SDDC compiles starting
portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-11-29 14:51:44 +00:00
2c54be651c Further updates
portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-11-28 22:31:44 +00:00
e859a199df Reduce volume to interior for coarse stencil -- worth up to 4x gain
portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-11-28 14:21:44 +00:00
0a3682ad0b MultiRHS work
portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-11-24 20:31:44 +00:00
59abaeb5cd Time stamp
portelli synced commits to refs/pull/379/merge at portelli/Grid from mirror 2023-11-24 12:21:43 +00:00
b391af4489 Merge 32e6d58356 into 7d077fe493
7d077fe493 Frontier compiel
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portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-11-24 04:11:44 +00:00
3e448435d3 Restrict to interior
a294bc3c5b Relax constraints for multiRHS
b302ad3d49 multiRHS test in place, passes Yay!
82fc4b1e94 Finalise
b4f1740380 Finalise message
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portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-11-16 00:11:44 +00:00
09946cf1ba Improved, works on 48^3 moving to multiRHS optimisations
f4fa95e7cb Use 5.3.0
100e29e35e Allow expression as argument to norm2
4cbe471a83 devVector
8bece1f861 Faster to transpose the matrix and apply with column major order
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portelli synced commits to develop at portelli/Grid from mirror 2023-11-09 21:11:43 +00:00
7d077fe493 Frontier compiel
portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-10-24 22:21:45 +01:00
4efa042f50 C++17 change
c7cb37e970 c++17 accepted
d34b207eab Avoid HIP warnings
0e6fa6f6b8 DOn't need the Cshift for the period optimisation
38b87de53f This works around a stacksize limit on AMD GPU
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portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-10-21 04:31:44 +01:00
351795ac3a Better messaging
9c9c42d0df Tests on frontier with real speed up . 3.5x on 16^3 at mq=0.01
b6ad1bafc7 Normal memory SendToRecvFrom asynchronous for use in general stencil
a5ca40f446 Better verbose -- track CPU GPU motion under --log Memory, others go to
9ab54c5565 Overlap comms & data copy/buffer assembly in Ghost zone exchange
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portelli synced commits to refs/pull/379/merge at portelli/Grid from mirror 2023-10-18 03:01:44 +01:00
dc87a9de71 Merge 32e6d58356 into 51051df62c
51051df62c 3GeV run setup
33097681b9 FTHMC compiled and merged to develop
07e4900218 FTHMC commit
36ab567d67 FTHMC 3 Gev
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portelli synced commits to develop at portelli/Grid from mirror 2023-10-17 02:31:44 +01:00
51051df62c 3GeV run setup
portelli synced commits to feature/scidac-wp1 at portelli/Grid from mirror 2023-10-17 02:31:44 +01:00
2207309f8a Spack rules