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If no f16c instructions supported must use software half precision conversion.
This will also become useful on BG/Q, so will move out from SSE4 into a general area. Lifted the Eigen half precision from web. Looks sensible, but not extensively regressed against the intrinsics implementation yet.
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paboyle
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26
configure.ac
26
configure.ac
@ -84,16 +84,15 @@ case ${ac_LAPACK} in
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esac
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############### FP16 conversions
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AC_ARG_ENABLE([fp16],
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[AC_HELP_STRING([--enable-fp16=yes|no], [enable fp16 comms])],
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[ac_FP16=${enable_fp16}], [ac_FP16=no])
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case ${ac_FP16} in
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no)
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;;
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AC_ARG_ENABLE([sfw-fp16],
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[AC_HELP_STRING([--enable-sfw-fp16=yes|no], [enable software fp16 comms])],
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[ac_SFW_FP16=${enable_sfw_fp16}], [ac_SFW_FP16=yes])
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case ${ac_SFW_FP16} in
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yes)
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AC_DEFINE([USE_FP16],[1],[conversion to fp16]);;
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AC_DEFINE([SFW_FP16],[1],[software conversion to fp16]);;
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no);;
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*)
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;;
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AC_MSG_ERROR(["SFW FP16 option not supported ${ac_SFW_FP16}"]);;
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esac
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############### MKL
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@ -189,7 +188,14 @@ case ${ax_cv_cxx_compiler_vendor} in
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case ${ac_SIMD} in
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SSE4)
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AC_DEFINE([SSE4],[1],[SSE4 intrinsics])
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SIMD_FLAGS='-msse4.2';;
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case ${ac_SFW_FP16} in
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yes)
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SIMD_FLAGS='-msse4.2';;
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no)
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SIMD_FLAGS='-msse4.2 -mf16c';;
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*)
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AC_MSG_ERROR(["SFW_FP16 must be either yes or no value ${ac_SFW_FP16} "]);;
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esac;;
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AVX)
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AC_DEFINE([AVX1],[1],[AVX intrinsics])
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SIMD_FLAGS='-mavx -mf16c';;
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@ -423,7 +429,6 @@ AC_OUTPUT
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echo "~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Summary of configuration for $PACKAGE v$VERSION
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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----- PLATFORM ----------------------------------------
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architecture (build) : $build_cpu
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os (build) : $build_os
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@ -436,6 +441,7 @@ SIMD : ${ac_SIMD}${SIMD_GEN_WIDTH_MSG}
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Threading : ${ac_openmp}
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Communications type : ${comms_type}
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Default precision : ${ac_PRECISION}
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Software FP16 conversion : ${ac_SFW_FP16}
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RNG choice : ${ac_RNG}
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GMP : `if test "x$have_gmp" = xtrue; then echo yes; else echo no; fi`
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LAPACK : ${ac_LAPACK}
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@ -38,7 +38,6 @@ Author: neo <cossu@post.kek.jp>
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#include <pmmintrin.h>
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namespace Grid {
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namespace Optimization {
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@ -333,26 +332,110 @@ namespace Optimization {
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#define _my_alignr_epi32(a,b,n) _mm_alignr_epi8(a,b,(n*4)%16)
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#define _my_alignr_epi64(a,b,n) _mm_alignr_epi8(a,b,(n*8)%16)
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#ifdef SFW_FP16
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struct Grid_half {
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Grid_half(){}
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Grid_half(uint16_t raw) : x(raw) {}
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uint16_t x;
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};
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union FP32 {
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unsigned int u;
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float f;
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};
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// PAB - Lifted and adapted from Eigen, which is GPL V2
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inline float sfw_half_to_float(Grid_half h) {
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const FP32 magic = { 113 << 23 };
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const unsigned int shifted_exp = 0x7c00 << 13; // exponent mask after shift
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FP32 o;
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o.u = (h.x & 0x7fff) << 13; // exponent/mantissa bits
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unsigned int exp = shifted_exp & o.u; // just the exponent
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o.u += (127 - 15) << 23; // exponent adjust
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// handle exponent special cases
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if (exp == shifted_exp) { // Inf/NaN?
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o.u += (128 - 16) << 23; // extra exp adjust
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} else if (exp == 0) { // Zero/Denormal?
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o.u += 1 << 23; // extra exp adjust
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o.f -= magic.f; // renormalize
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}
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o.u |= (h.x & 0x8000) << 16; // sign bit
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return o.f;
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}
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inline Grid_half sfw_float_to_half(float ff) {
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FP32 f; f.f = ff;
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const FP32 f32infty = { 255 << 23 };
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const FP32 f16max = { (127 + 16) << 23 };
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const FP32 denorm_magic = { ((127 - 15) + (23 - 10) + 1) << 23 };
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unsigned int sign_mask = 0x80000000u;
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Grid_half o;
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o.x = static_cast<unsigned short>(0x0u);
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unsigned int sign = f.u & sign_mask;
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f.u ^= sign;
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// NOTE all the integer compares in this function can be safely
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// compiled into signed compares since all operands are below
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// 0x80000000. Important if you want fast straight SSE2 code
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// (since there's no unsigned PCMPGTD).
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if (f.u >= f16max.u) { // result is Inf or NaN (all exponent bits set)
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o.x = (f.u > f32infty.u) ? 0x7e00 : 0x7c00; // NaN->qNaN and Inf->Inf
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} else { // (De)normalized number or zero
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if (f.u < (113 << 23)) { // resulting FP16 is subnormal or zero
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// use a magic value to align our 10 mantissa bits at the bottom of
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// the float. as long as FP addition is round-to-nearest-even this
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// just works.
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f.f += denorm_magic.f;
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// and one integer subtract of the bias later, we have our final float!
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o.x = static_cast<unsigned short>(f.u - denorm_magic.u);
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} else {
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unsigned int mant_odd = (f.u >> 13) & 1; // resulting mantissa is odd
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// update exponent, rounding bias part 1
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f.u += ((unsigned int)(15 - 127) << 23) + 0xfff;
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// rounding bias part 2
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f.u += mant_odd;
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// take the bits!
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o.x = static_cast<unsigned short>(f.u >> 13);
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}
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}
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o.x |= static_cast<unsigned short>(sign >> 16);
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return o;
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}
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static inline __m128i Grid_mm_cvtps_ph(__m128 f,int discard) {
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__m128i ret=(__m128i)_mm_setzero_ps();
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float *fp = (float *)&f;
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Grid_half *hp = (Grid_half *)&ret;
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hp[0] = sfw_float_to_half(fp[0]);
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hp[1] = sfw_float_to_half(fp[1]);
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hp[2] = sfw_float_to_half(fp[2]);
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hp[3] = sfw_float_to_half(fp[3]);
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return ret;
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}
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static inline __m128i Grid_mm_cvtph_ps(__m128i h,int discard) {
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__m128 ret=_mm_setzero_ps();
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float *fp = (float *)&ret;
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Grid_half *hp = (Grid_half *)&h;
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fp[0] = sfw_half_to_float(hp[0]);
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fp[1] = sfw_half_to_float(hp[1]);
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fp[2] = sfw_half_to_float(hp[2]);
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fp[3] = sfw_half_to_float(hp[3]);
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return ret;
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}
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#else
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#define Grid_mm_cvtps_ph _mm_cvtps_ph
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#define Grid_mm_cvtph_ps _mm_cvtph_ps
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#endif
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struct PrecisionChange {
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static inline __m128i StoH (__m128 a,__m128 b) {
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#ifdef USE_FP16
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__m128i ha = _mm_cvtps_ph(a,0);
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__m128i hb = _mm_cvtps_ph(b,0);
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__m128i ha = Grid_mm_cvtps_ph(a,0);
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__m128i hb = Grid_mm_cvtps_ph(b,0);
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__m128i h =(__m128i) _mm_shuffle_ps((__m128)ha,(__m128)hb,_MM_SELECT_FOUR_FOUR(1,0,1,0));
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#else
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__m128i h = (__m128i)a;
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assert(0);
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#endif
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return h;
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}
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static inline void HtoS (__m128i h,__m128 &sa,__m128 &sb) {
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#ifdef USE_FP16
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sa = _mm_cvtph_ps(h);
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sa = Grid_mm_cvtph_ps(h,0);
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h = (__m128i)_my_alignr_epi32((__m128i)h,(__m128i)h,2);
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sb = _mm_cvtph_ps(h);
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#else
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assert(0);
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#endif
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sb = Grid_mm_cvtph_ps(h,0);
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}
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static inline __m128 DtoS (__m128d a,__m128d b) {
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__m128 sa = _mm_cvtpd_ps(a);
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