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https://github.com/paboyle/Grid.git
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Merge branch 'feature/gpu-port' of https://github.com/paboyle/Grid into feature/gpu-port
Conflicts: Grid/stencil/Stencil.h
This commit is contained in:
Peter Boyle
commit
705a8098b2
@ -62,7 +62,7 @@ public:
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LatticeCoordinate(coor, nu + shift);
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ph = ph + twist[nu]*coor*((1./(in.Grid()->FullDimensions()[nu+shift])));
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}
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in_buf = exp((Real)(2.0*M_PI)*ci*ph*(-1.0))*in;
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in_buf = exp(Scalar(2.0*M_PI)*ci*ph*(-1.0))*in;
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if(fiveD){//FFT only on temporal and spatial dimensions
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std::vector<int> mask(Nd+1,1); mask[0] = 0;
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@ -77,7 +77,7 @@ public:
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}
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//phase for boundary condition
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out = out * exp((Real)(2.0*M_PI)*ci*ph);
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out = out * exp(Scalar(2.0*M_PI)*ci*ph);
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};
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virtual void FreePropagator(const FermionField &in,FermionField &out,RealD mass,std::vector<double> twist) {
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@ -323,10 +323,8 @@ public:
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this->HaloExchangeOptGather(source,compress);
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double t1=usecond();
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// Asynchronous MPI calls multidirectional, Isend etc...
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// this->CommunicateBegin(reqs);
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// this->CommunicateComplete(reqs);
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// Non-overlapped directions within a thread. Asynchronous calls except MPI3, threaded up to comm threads ways.
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this->Communicate();
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// this->Communicate();
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double t2=usecond(); timer1 += t2-t1;
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this->CommsMerge(compress);
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double t3=usecond(); timer2 += t3-t2;
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@ -1 +0,0 @@
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../CayleyFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../ContinuedFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../DomainWallEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../MobiusEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../PartialFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonCloverFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonKernelsInstantiationGparity.cc.master
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@ -1 +0,0 @@
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../WilsonTMFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../CayleyFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../ContinuedFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../DomainWallEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../MobiusEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../PartialFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonCloverFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonKernelsInstantiationGparity.cc.master
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@ -1 +0,0 @@
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../WilsonTMFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../CayleyFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../ContinuedFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../DomainWallEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../MobiusEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../PartialFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonCloverFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonKernelsInstantiationGparity.cc.master
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@ -1 +0,0 @@
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../WilsonTMFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../CayleyFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../ContinuedFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../DomainWallEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../MobiusEOFAFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../PartialFractionFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonCloverFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermion5DInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonFermionInstantiation.cc.master
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@ -1 +0,0 @@
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../WilsonKernelsInstantiationGparity.cc.master
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@ -1 +0,0 @@
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../WilsonTMFermionInstantiation.cc.master
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@ -777,7 +777,7 @@ public:
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int permute_slice=0;
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if(permute_dim){
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int wrap = sshift/rd;
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int wrap = sshift/rd; wrap=wrap % ly; // but it is local anyway
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int num = sshift%rd;
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if ( x< rd-num ) permute_slice=wrap;
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else permute_slice = (wrap+1)%ly;
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@ -69,6 +69,11 @@ void coalescedWrite(vobj & __restrict__ vec,const vobj & __restrict__ extracted,
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// vstream(vec, extracted);
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vec = extracted;
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}
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template<class vobj> accelerator_inline
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void coalescedWriteNonTemporal(vobj & __restrict__ vec,const vobj & __restrict__ extracted,int lane=0)
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{
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vstream(vec, extracted);
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}
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#else
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accelerator_inline int SIMTlane(int Nsimd) { return threadIdx.y; } // CUDA specific
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@ -92,6 +97,11 @@ void coalescedWrite(vobj & __restrict__ vec,const typename vobj::scalar_object &
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{
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insertLane(lane,vec,extracted);
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}
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template<class vobj> accelerator_inline
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void coalescedWriteNonTemporal(vobj & __restrict__ vec,const vobj & __restrict__ extracted,int lane=0)
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{
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insertLane(lane,vec,extracted);
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}
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#endif
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50
TODO
50
TODO
@ -1,66 +1,58 @@
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- Lattice_arith - are the mult, mac etc.. still needed after ET engine?
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- LinalgUtils ssp loop not offloaded
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- Mobius/Domain EOFA cache header implementaiotn has thread_loop
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- ImprovedStaggered accelerate
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- Lattice_reduction - remnant thread_loops must offload. Audit thread_loop in main code for non-accelerated code
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Lattice_rng
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Lattice_transfer.h
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- Stencil.h : Thread loops in exchange code. Need to offload these
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- Lebesque order reintroduction. StencilView should have pointer
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- accelerate A2Autils
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- accelerate A2Autils -- off critical path for HMC
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- Lebesque order reintroduction. StencilView should have pointer to it
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GPU branch code item work list
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-----------------------------
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7) Accelerate the cshift
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7) Accelerate the cshift & benchmark
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* 0) Single GPU
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- 128 bit integer table load in GPU code.
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- coalescedRead <- threadIdx.x
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- Gianluca's changes to Cayley into gpu-port
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- GPU accelerate EOFA
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- Staggered kernels -> GPU coalesced loop
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- Staggered kernels -> GPU coalesced loop, loop in kernels
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- Staggered kernels inline for GPU -- DONE
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* 2) 5D terms & Gianluca
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* Gianluca merger
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- Cayley coefficients -> GPU retention or prefetch
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- Mobius kernel fusion. -- Gianluca?
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- Make GPU offload reductions optionally deterministic -- Gianluca
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- Gianluca's changes to Cayley into gpu-port
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- Mobius kernel fusion. -- Gianluca?
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- Make GPU offload reductions deterministic -- Gianluca merge
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- Lattice_reduction - remnant thread_loops must offload. Audit thread_loop in main code for non-accelerated code
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* 3) Comms/NVlink
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- OpenMP tasks to run comms threads.
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- OpenMP tasks to run comms threads. Experiment with it
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- Remove explicit openMP in staggered.
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- Single parallel region around both the Kernel call
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and the comms.
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- Single parallel region around both the Kernel call and the comms.
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- Fix the halo exchange SIMT loop
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- Stencil gather
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- Stencil gather ??
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- SIMD dirs in stencil
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* 4) ET enhancements
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- eval -> scalar ops in ET engine
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- coalescedRead, coalescedWrite in expressions.
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- coalescedRead, coalescedWrite in expressions.
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* 5) Misc
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- Conserved current clean up.
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- multLinkProp eliminate
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8) Merge develop and test HMC
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9) Gamma tables on GPU; check this.
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9) Gamma tables on GPU; check this. Appear to work, but no idea why. Are these done on CPU?
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10) Audit
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- pragma once uniformly
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- Audit NAMESPACE CHANGES
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- Audit changes
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=============================================================================================
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- GPU accelerate EOFA -- DONE
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- LinalgUtils ssp loop not offloaded -- DONE
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- coalescedRead <- threadIdx.x -- DONE
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- Stencil.h : Thread loops in exchange code. Need to offload these -- DONE ; pending debug
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- Mobius/Domain EOFA cache header implementaiotn has thread_loop -- DONE ; pending test
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- Differentiate non-temporal coalescedWrite from temporal -- DONE
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- Clean up PRAGMAS, and SIMT_loop -- DONE
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thread_loop interface revisit.
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_foreach
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