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https://github.com/paboyle/Grid.git
synced 2024-09-20 09:15:38 +01:00
re-introduced HOTFIX cause Grid binaries give wrong results otherwise; checked in good gridverter.py
This commit is contained in:
nils meyer
parent
6504a098cc
commit
852db4626a
@ -118,7 +118,7 @@ accelerator_inline Grid_half sfw_float_to_half(float ff) {
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#ifdef GEN
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#if defined(A64FX) // breakout A64FX SVE ACLE here
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//#pragma message("building for A64FX / SVE ACLE")
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//#define ARMCLANGHOTFIX
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#define ARMCLANGHOTFIX
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#include "Grid_a64fx-2.h"
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#else
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#include "Grid_generic.h"
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@ -47,7 +47,7 @@ ALTERNATIVE_LOADS = False
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# must use with my_wilson4.h and my_wilson4pf.h
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ALTERNATIVE_REGISTER_MAPPING = False
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ALTERNATIVE_REGISTER_MAPPING = not ALTERNATIVE_REGISTER_MAPPING
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#ALTERNATIVE_REGISTER_MAPPING = not ALTERNATIVE_REGISTER_MAPPING
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if ALTERNATIVE_REGISTER_MAPPING == True:
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ALTERNATIVE_LOADS = False
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@ -229,15 +229,25 @@ class Register:
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gpr = d['asmtableptr']
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cast = 'uint64_t'
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asm_opcode = 'ld1d'
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#asm_opcode = 'ld1d'
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#if PRECISION == 'single':
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# asm_opcode = 'ld1w'
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# cast = 'uint32_t'
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asm_opcode = 'ldr'
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if PRECISION == 'single':
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asm_opcode = 'ld1w'
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asm_opcode = 'ldr'
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cast = 'uint32_t'
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d['I'] += F' {self.name} = svld1(pg1, ({cast}*)&lut[{t}]); \\\n'
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# using immediate index break-out works
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d['A'] += F' "{asm_opcode} {{ {self.asmregwithsuffix} }}, {pg1.asmreg}/z, [%[tableptr], %[index], mul vl] \\n\\t" \\\n'
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if asm_opcode == 'ldr':
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# ldr version
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d['A'] += F' "{asm_opcode} {self.asmreg}, [%[tableptr], %[index], mul vl] \\n\\t" \\\n'
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else:
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# ld1 version
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d['A'] += F' "{asm_opcode} {{ {self.asmregwithsuffix} }}, {pg1.asmreg}/z, [%[tableptr], %[index], mul vl] \\n\\t" \\\n'
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d['asminput'].append(F'[tableptr] "r" (&lut[0])')
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d['asminput'].append(F'[index] "i" ({t})')
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d['asmclobber'].append(F'"memory"')
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@ -249,9 +259,14 @@ class Register:
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indices = re.findall(r'\d+', address)
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index = (int(indices[0]) - offset) * colors + int(indices[1])
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asm_opcode = 'ld1d'
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#asm_opcode = 'ld1d'
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#if PRECISION == 'single':
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#asm_opcode = 'ld1w'
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# cast = 'float32_t'
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asm_opcode = 'ldr'
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if PRECISION == 'single':
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asm_opcode = 'ld1w'
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asm_opcode = 'ldr'
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cast = 'float32_t'
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gpr = d['asmfetchbaseptr']
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@ -259,9 +274,13 @@ class Register:
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if (target in ['ALL', 'C']):
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d['C'] += F' {self.name} = {address}; \\\n'
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if (target in ['ALL', 'I']):
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# d['I'] += F' {self.name} = svldnt1(pg1, ({cast}*)({intrinfetchbase} + {index} * 64)); \\\n'
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d['I'] += F' {self.name} = svld1(pg1, ({cast}*)({intrinfetchbase} + {index} * 64)); \\\n'
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if (target in ['ALL', 'A']):
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d['A'] += F' "{asm_opcode} {{ {self.asmregwithsuffix} }}, {pg1.asmreg}/z, [%[fetchptr], {index}, mul vl] \\n\\t" \\\n'
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if asm_opcode == 'ldr':
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d['A'] += F' "{asm_opcode} {self.asmreg}, [%[fetchptr], {index}, mul vl] \\n\\t" \\\n'
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else:
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d['A'] += F' "{asm_opcode} {{ {self.asmregwithsuffix} }}, {pg1.asmreg}/z, [%[fetchptr], {index}, mul vl] \\n\\t" \\\n'
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def store(self, address, cast='float64_t', colors=3, offset=STORE_BASE_PTR_COLOR_OFFSET):
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global d
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@ -269,16 +288,24 @@ class Register:
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indices = re.findall(r'\d+', address)
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index = (int(indices[0]) - offset) * colors + int(indices[1])
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asm_opcode = 'stnt1d'
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#asm_opcode = 'stnt1d'
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#if PRECISION == 'single':
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# asm_opcode = 'stnt1w'
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# cast = 'float32_t'
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asm_opcode = 'str'
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if PRECISION == 'single':
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asm_opcode = 'stnt1w'
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asm_opcode = 'str'
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cast = 'float32_t'
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intrinstorebase = d['intrinstorebase']
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d['C'] += F' {address} = {self.name}; \\\n'
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d['I'] += F' svstnt1(pg1, ({cast}*)({intrinstorebase} + {index} * 64), {self.name}); \\\n'
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d['A'] += F' "{asm_opcode} {{ {self.asmregwithsuffix} }}, {pg1.asmreg}, [%[storeptr], {index}, mul vl] \\n\\t" \\\n'
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#d['I'] += F' svstnt1(pg1, ({cast}*)({intrinstorebase} + {index} * 64), {self.name}); \\\n'
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d['I'] += F' svst1(pg1, ({cast}*)({intrinstorebase} + {index} * 64), {self.name}); \\\n'
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if asm_opcode == 'str':
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d['A'] += F' "{asm_opcode} {self.asmreg}, [%[storeptr], {index}, mul vl] \\n\\t" \\\n'
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else:
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d['A'] += F' "{asm_opcode} {{ {self.asmregwithsuffix} }}, {pg1.asmreg}, [%[storeptr], {index}, mul vl] \\n\\t" \\\n'
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def movestr(self, str):
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global d
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@ -621,7 +648,16 @@ def prefetch_L2_store(address, offset):
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d['I'] += F' svprfd(pg1, (int64_t*)({address} + {offset * multiplier * 64}), SV_{policy}); \\\n'
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d['A'] += F' "prfd {policy}, {pg1.asmreg}, [%[fetchptr], {offset * multiplier}, mul vl] \\n\\t" \\\n'
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#d['A'] +=
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def prefetch_L1_store(address, offset):
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global d
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multiplier = 4 # offset in CL, have to multiply by 4
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policy = "PSTL1STRM" # weak
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#policy = "PSTL2KEEP" # strong
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d['I'] += F' svprfd(pg1, (int64_t*)({address} + {offset * multiplier * 64}), SV_{policy}); \\\n'
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d['A'] += F' "prfd {policy}, {pg1.asmreg}, [%[fetchptr], {offset * multiplier}, mul vl] \\n\\t" \\\n'
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def asmopen():
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#write('asm volatile ( \\', target='A')
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@ -878,9 +914,11 @@ if PREFETCH:
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define(F'PREFETCH_GAUGE_L2(A) PREFETCH_GAUGE_L2_INTERNAL_{PRECSUFFIX}(A)')
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define(F'PF_GAUGE(A)')
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define(F'PREFETCH_RESULT_L2_STORE(A) PREFETCH_RESULT_L2_STORE_INTERNAL_{PRECSUFFIX}(A)')
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define(F'PREFETCH_RESULT_L1_STORE(A) PREFETCH_RESULT_L1_STORE_INTERNAL_{PRECSUFFIX}(A)')
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define(F'PREFETCH1_CHIMU(A) PREFETCH_CHIMU_L1(A)')
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# define(F'PREFETCH1_CHIMU(A)')
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define(F'PREFETCH_CHIMU(A) PREFETCH_CHIMU_L1(A)')
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# define(F'PREFETCH_CHIMU(A)')
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else:
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define(F'PREFETCH_CHIMU_L1(A)')
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define(F'PREFETCH_GAUGE_L1(A)')
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@ -897,8 +935,9 @@ define(F'UNLOCK_GAUGE(A)')
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define(F'MASK_REGS DECLARATIONS_{PRECSUFFIX}')
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define(F'COMPLEX_SIGNS(A)')
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define(F'LOAD64(A,B)')
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#define(F'SAVE_RESULT(A,B) RESULT_{PRECSUFFIX}(A); PREFETCH_RESULT_L2_STORE(B);')
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define(F'SAVE_RESULT(A,B) RESULT_{PRECSUFFIX}(A); PREFETCH_CHIMU_L1(B);')
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# prefetch chimu here is useless, because already done in last leg
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#define(F'SAVE_RESULT(A,B) RESULT_{PRECSUFFIX}(A);')
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define(F'SAVE_RESULT(A,B) RESULT_{PRECSUFFIX}(A); PREFETCH_RESULT_L2_STORE(B);')
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if PREFETCH:
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definemultiline(F'MULT_2SPIN_DIR_PF(A,B) ')
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write (F' MULT_2SPIN_{PRECSUFFIX}(A); \\')
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@ -2156,8 +2195,7 @@ asmclose()
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#debugall('ZERO_PSI', group='result')
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newline()
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d['factor'] = 0
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# prefetch store spinors into L2 cache
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# prefetch store spinors to L2 cache
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d['factor'] = 0
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d['cycles_PREFETCH_L2'] += 0 * d['factor']
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write('// PREFETCH_RESULT_L2_STORE (prefetch store to L2)')
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@ -2173,6 +2211,23 @@ asmclose()
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curlyclose()
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newline()
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# prefetch store spinors to L1 cache
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d['factor'] = 0
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d['cycles_PREFETCH_L1'] += 0 * d['factor']
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write('// PREFETCH_RESULT_L1_STORE (prefetch store to L1)')
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definemultiline(F'PREFETCH_RESULT_L1_STORE_INTERNAL_{PRECSUFFIX}(base)')
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curlyopen()
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fetch_base_ptr(F"base")
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asmopen()
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fetch_base_ptr(F"base", target='A')
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prefetch_L1_store(F"base", 0)
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prefetch_L1_store(F"base", 1)
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prefetch_L1_store(F"base", 2)
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asmclose()
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curlyclose()
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newline()
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d['factor'] = 0
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write('// ADD_RESULT_INTERNAL')
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definemultiline(F'ADD_RESULT_INTERNAL_{PRECSUFFIX}')
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