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Move coalesced read into tensors
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@ -56,44 +56,6 @@ NAMESPACE_BEGIN(Grid);
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// Gather for when there *is* need to SIMD split with compression
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///////////////////////////////////////////////////////////////////
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#ifdef __CUDA_ARCH__
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//////////////////////////////////////////
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// EExtract and insert slices on the GPU
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//////////////////////////////////////////
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template<class vobj> accelerator_inline
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typename vobj::scalar_object coalescedRead(const vobj & __restrict__ vec)
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{
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typedef typename vobj::scalar_type scalar_type;
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typedef typename vobj::vector_type vector_type;
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constexpr int Nsimd = sizeof(vector_type)/sizeof(scalar_type);
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int lane = threadIdx.x % Nsimd;
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return extractLane(lane,vec);
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}
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template<class vobj> accelerator_inline
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void coalescedWrite(vobj & __restrict__ vec,const typename vobj::scalar_object & __restrict__ extracted)
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{
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typedef typename vobj::scalar_type scalar_type;
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typedef typename vobj::vector_type vector_type;
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constexpr int Nsimd = sizeof(vector_type)/sizeof(scalar_type);
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int lane = threadIdx.x % Nsimd;
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insertLane(lane,vec,extracted);
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}
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#else
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//////////////////////////////////////////
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// Trivial mapping of vectors on host
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//////////////////////////////////////////
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template<class vobj> accelerator_inline
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vobj coalescedRead(const vobj & __restrict__ vec)
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{
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return vec;
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}
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template<class vobj> accelerator_inline
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void coalescedWrite(vobj & __restrict__ vec,const vobj & __restrict__ extracted)
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{
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vec = extracted;
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}
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#endif
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void Gather_plane_table_compute (GridBase *grid,int dimension,int plane,int cbmask,
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int off,Vector<std::pair<int,int> > & table);
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