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Zmobius asm
This commit is contained in:
Peter Boyle
parent
55cb22ad67
commit
fa6acccf55
@ -514,7 +514,8 @@ template<class Impl>
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void CayleyFermion5D<Impl>::MooeeInternalZAsm(const FermionField &psi, FermionField &chi,
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int LLs, int site, Vector<iSinglet<Simd> > &Matp, Vector<iSinglet<Simd> > &Matm)
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{
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#if 1
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#ifndef AVX512
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//#if 0
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{
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SiteHalfSpinor BcastP;
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SiteHalfSpinor BcastM;
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@ -542,12 +543,13 @@ void CayleyFermion5D<Impl>::MooeeInternalZAsm(const FermionField &psi, FermionFi
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for(int co=0;co<Nc;co++){
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vbroadcast(BcastM()(sp )(co),psi[lex]()(sp+2)(co),l);
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}}
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if ( s2==0 && l==0) {
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for(int sp=0;sp<2;sp++){
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for(int co=0;co<Nc;co++){
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SiteChiP()(sp)(co)=SiteChiP()(sp)(co)+ Matp[LLs*s+s1]()()()*BcastP()(sp)(co);
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SiteChiM()(sp)(co)=SiteChiM()(sp)(co)+ Matm[LLs*s+s1]()()()*BcastM()(sp)(co);
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}}
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}
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}}
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{
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@ -564,7 +566,7 @@ void CayleyFermion5D<Impl>::MooeeInternalZAsm(const FermionField &psi, FermionFi
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#else
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{
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// pointers
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// MASK_REGS;
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// MASK_REGS;
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#define Chi_00 %zmm0
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#define Chi_01 %zmm1
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#define Chi_02 %zmm2
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@ -577,20 +579,37 @@ void CayleyFermion5D<Impl>::MooeeInternalZAsm(const FermionField &psi, FermionFi
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#define Chi_30 %zmm9
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#define Chi_31 %zmm10
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#define Chi_32 %zmm11
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#define pChi_00 %%zmm0
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#define pChi_01 %%zmm1
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#define pChi_02 %%zmm2
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#define pChi_10 %%zmm3
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#define pChi_11 %%zmm4
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#define pChi_12 %%zmm5
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#define pChi_20 %%zmm6
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#define pChi_21 %%zmm7
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#define pChi_22 %%zmm8
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#define pChi_30 %%zmm9
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#define pChi_31 %%zmm10
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#define pChi_32 %%zmm11
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#define BCAST0 %zmm12
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#define BCAST1 %zmm13
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#define BCAST2 %zmm14
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#define BCAST3 %zmm15
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#define BCAST4 %zmm16
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#define BCAST5 %zmm17
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#define BCAST6 %zmm18
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#define BCAST7 %zmm19
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#define BCAST8 %zmm20
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#define BCAST9 %zmm21
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#define BCAST10 %zmm22
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#define BCAST11 %zmm23
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#define BCAST_00 %zmm12
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#define SHUF_00 %zmm13
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#define BCAST_01 %zmm14
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#define SHUF_01 %zmm15
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#define BCAST_02 %zmm16
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#define SHUF_02 %zmm17
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#define BCAST_10 %zmm18
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#define SHUF_10 %zmm19
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#define BCAST_11 %zmm20
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#define SHUF_11 %zmm21
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#define BCAST_12 %zmm22
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#define SHUF_12 %zmm23
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#define Mp %zmm24
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#define Mps %zmm25
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#define Mm %zmm26
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#define Mms %zmm27
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#define N 8
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int incr=LLs*LLs*sizeof(iSinglet<Simd>);
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for(int s1=0;s1<LLs;s1++){
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for(int s2=0;s2<LLs;s2++){
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@ -604,67 +623,80 @@ void CayleyFermion5D<Impl>::MooeeInternalZAsm(const FermionField &psi, FermionFi
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LOAD64(%r9,a1);
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LOAD64(%r10,a2);
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asm (
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VPREFETCH1(0,%r10) VPREFETCH1(0,%r9)
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VPREFETCH1(12,%r10) VPREFETCH1(13,%r10)
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VPREFETCH1(14,%r10) VPREFETCH1(15,%r10)
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VBCASTCDUP(0,%r10,BCAST0) VBCASTCDUP(1,%r10,BCAST1)
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VBCASTCDUP(2,%r10,BCAST2) VBCASTCDUP(3,%r10,BCAST3)
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VBCASTCDUP(4,%r10,BCAST4) VBCASTCDUP(5,%r10,BCAST5)
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VBCASTCDUP(6,%r10,BCAST6) VBCASTCDUP(7,%r10,BCAST7)
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VBCASTCDUP(8,%r10,BCAST8) VBCASTCDUP(9,%r10,BCAST9)
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VBCASTCDUP(10,%r10,BCAST10) VBCASTCDUP(11,%r10,BCAST11)
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VMULIDUP (0,%r8,BCAST0,Chi_00) VMULIDUP(0,%r8,BCAST1,Chi_01) // II RI from Mat / Psi
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VMULIDUP (0,%r8,BCAST2,Chi_02) VMULIDUP(0,%r8,BCAST3,Chi_10)
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VMULIDUP (0,%r8,BCAST4,Chi_11) VMULIDUP(0,%r8,BCAST5,Chi_12)
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VMULIDUP (0,%r9,BCAST6,Chi_20) VMULIDUP(0,%r9,BCAST7,Chi_21)
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VMULIDUP (0,%r9,BCAST8,Chi_22) VMULIDUP(0,%r9,BCAST9,Chi_30)
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VMULIDUP (0,%r9,BCAST10,Chi_31) VMULIDUP(0,%r9,BCAST11,Chi_32)
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VSHUF(BCAST0,BCAST0) VSHUF(BCAST1,BCAST1)
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VSHUF(BCAST2,BCAST2) VSHUF(BCAST3,BCAST3)
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VSHUF(BCAST4,BCAST4) VSHUF(BCAST5,BCAST5)
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VSHUF(BCAST6,BCAST6) VSHUF(BCAST7,BCAST7)
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VSHUF(BCAST8,BCAST8) VSHUF(BCAST9,BCAST9)
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VSHUF(BCAST10,BCAST10) VSHUF(BCAST11,BCAST11)
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VMADDSUBRDUP(0,%r8,BCAST0,Chi_00) VMADDSUBRDUP(0,%r8,BCAST1,Chi_01)
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VMADDSUBRDUP(0,%r8,BCAST2,Chi_02) VMADDSUBRDUP(0,%r8,BCAST3,Chi_10)
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VMADDSUBRDUP(0,%r8,BCAST4,Chi_11) VMADDSUBRDUP(0,%r8,BCAST5,Chi_12)
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VMADDSUBRDUP(0,%r9,BCAST6,Chi_20) VMADDSUBRDUP(0,%r9,BCAST7,Chi_21)
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VMADDSUBRDUP(0,%r9,BCAST8,Chi_22) VMADDSUBRDUP(0,%r9,BCAST9,Chi_30)
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VMADDSUBRDUP(0,%r9,BCAST10,Chi_31) VMADDSUBRDUP(0,%r9,BCAST11,Chi_32) );
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VLOAD(0,%r8,Mp)// i r
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VLOAD(0,%r9,Mm)
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VSHUF(Mp,Mps) // r i
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VSHUF(Mm,Mms)
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VPREFETCH1(12,%r10) VPREFETCH1(13,%r10)
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VPREFETCH1(14,%r10) VPREFETCH1(15,%r10)
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VMULIDUP(0*N,%r10,Mps,Chi_00)
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VMULIDUP(1*N,%r10,Mps,Chi_01)
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VMULIDUP(2*N,%r10,Mps,Chi_02)
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VMULIDUP(3*N,%r10,Mps,Chi_10)
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VMULIDUP(4*N,%r10,Mps,Chi_11)
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VMULIDUP(5*N,%r10,Mps,Chi_12)
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VMULIDUP(6*N ,%r10,Mms,Chi_20)
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VMULIDUP(7*N ,%r10,Mms,Chi_21)
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VMULIDUP(8*N ,%r10,Mms,Chi_22)
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VMULIDUP(9*N ,%r10,Mms,Chi_30)
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VMULIDUP(10*N,%r10,Mms,Chi_31)
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VMULIDUP(11*N,%r10,Mms,Chi_32)
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VMADDSUBRDUP(0*N,%r10,Mp,Chi_00)
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VMADDSUBRDUP(1*N,%r10,Mp,Chi_01)
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VMADDSUBRDUP(2*N,%r10,Mp,Chi_02)
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VMADDSUBRDUP(3*N,%r10,Mp,Chi_10)
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VMADDSUBRDUP(4*N,%r10,Mp,Chi_11)
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VMADDSUBRDUP(5*N,%r10,Mp,Chi_12)
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VMADDSUBRDUP(6*N ,%r10,Mm,Chi_20)
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VMADDSUBRDUP(7*N ,%r10,Mm,Chi_21)
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VMADDSUBRDUP(8*N ,%r10,Mm,Chi_22)
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VMADDSUBRDUP(9*N ,%r10,Mm,Chi_30)
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VMADDSUBRDUP(10*N,%r10,Mm,Chi_31)
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VMADDSUBRDUP(11*N,%r10,Mm,Chi_32)
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);
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} else {
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LOAD64(%r8,a0);
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LOAD64(%r9,a1);
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LOAD64(%r10,a2);
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asm (
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VPREFETCH1(0,%r10) VPREFETCH1(0,%r9)
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VPREFETCH1(12,%r10) VPREFETCH1(13,%r10)
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VPREFETCH1(14,%r10) VPREFETCH1(15,%r10)
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VBCASTCDUP(0,%r10,BCAST0) VBCASTCDUP(1,%r10,BCAST1)
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VBCASTCDUP(2,%r10,BCAST2) VBCASTCDUP(3,%r10,BCAST3)
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VBCASTCDUP(4,%r10,BCAST4) VBCASTCDUP(5,%r10,BCAST5)
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VBCASTCDUP(6,%r10,BCAST6) VBCASTCDUP(7,%r10,BCAST7)
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VBCASTCDUP(8,%r10,BCAST8) VBCASTCDUP(9,%r10,BCAST9)
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VBCASTCDUP(10,%r10,BCAST10) VBCASTCDUP(11,%r10,BCAST11)
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VMADDSUBIDUP (0,%r8,BCAST0,Chi_00) VMADDSUBIDUP(0,%r8,BCAST1,Chi_01) // II RI from Mat / Psi
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VMADDSUBIDUP (0,%r8,BCAST2,Chi_02) VMADDSUBIDUP(0,%r8,BCAST3,Chi_10)
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VMADDSUBIDUP (0,%r8,BCAST4,Chi_11) VMADDSUBIDUP(0,%r8,BCAST5,Chi_12)
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VMADDSUBIDUP (0,%r9,BCAST6,Chi_20) VMADDSUBIDUP(0,%r9,BCAST7,Chi_21)
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VMADDSUBIDUP (0,%r9,BCAST8,Chi_22) VMADDSUBIDUP(0,%r9,BCAST9,Chi_30)
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VMADDSUBIDUP (0,%r9,BCAST10,Chi_31) VMADDSUBIDUP(0,%r9,BCAST11,Chi_32)
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VSHUF(BCAST0,BCAST0) VSHUF(BCAST1,BCAST1)
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VSHUF(BCAST2,BCAST2) VSHUF(BCAST3,BCAST3)
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VSHUF(BCAST4,BCAST4) VSHUF(BCAST5,BCAST5)
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VSHUF(BCAST6,BCAST6) VSHUF(BCAST7,BCAST7)
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VSHUF(BCAST8,BCAST8) VSHUF(BCAST9,BCAST9)
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VSHUF(BCAST10,BCAST10) VSHUF(BCAST11,BCAST11)
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VMADDSUBRDUP(0,%r8,BCAST0,Chi_00) VMADDSUBRDUP(0,%r8,BCAST1,Chi_01)
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VMADDSUBRDUP(0,%r8,BCAST2,Chi_02) VMADDSUBRDUP(0,%r8,BCAST3,Chi_10)
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VMADDSUBRDUP(0,%r8,BCAST4,Chi_11) VMADDSUBRDUP(0,%r8,BCAST5,Chi_12)
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VMADDSUBRDUP(0,%r9,BCAST6,Chi_20) VMADDSUBRDUP(0,%r9,BCAST7,Chi_21)
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VMADDSUBRDUP(0,%r9,BCAST8,Chi_22) VMADDSUBRDUP(0,%r9,BCAST9,Chi_30)
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VMADDSUBRDUP(0,%r9,BCAST10,Chi_31) VMADDSUBRDUP(0,%r9,BCAST11,Chi_32)
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);
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VLOAD(0,%r8,Mp)
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VSHUF(Mp,Mps)
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VLOAD(0,%r9,Mm)
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VSHUF(Mm,Mms)
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VMADDSUBIDUP(0*N,%r10,Mps,Chi_00) // Mri * Pii +- Cir
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VMADDSUBIDUP(1*N,%r10,Mps,Chi_01)
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VMADDSUBIDUP(2*N,%r10,Mps,Chi_02)
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VMADDSUBIDUP(3*N,%r10,Mps,Chi_10)
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VMADDSUBIDUP(4*N,%r10,Mps,Chi_11)
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VMADDSUBIDUP(5*N,%r10,Mps,Chi_12)
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VMADDSUBIDUP(6 *N,%r10,Mms,Chi_20)
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VMADDSUBIDUP(7 *N,%r10,Mms,Chi_21)
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VMADDSUBIDUP(8 *N,%r10,Mms,Chi_22)
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VMADDSUBIDUP(9 *N,%r10,Mms,Chi_30)
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VMADDSUBIDUP(10*N,%r10,Mms,Chi_31)
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VMADDSUBIDUP(11*N,%r10,Mms,Chi_32)
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VMADDSUBRDUP(0*N,%r10,Mp,Chi_00) // Cir = Mir * Prr +- ( Mri * Pii +- Cir)
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VMADDSUBRDUP(1*N,%r10,Mp,Chi_01) // Ci = MiPr + Ci + MrPi ; Cr = MrPr - ( MiPi - Cr)
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VMADDSUBRDUP(2*N,%r10,Mp,Chi_02)
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VMADDSUBRDUP(3*N,%r10,Mp,Chi_10)
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VMADDSUBRDUP(4*N,%r10,Mp,Chi_11)
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VMADDSUBRDUP(5*N,%r10,Mp,Chi_12)
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VMADDSUBRDUP(6 *N,%r10,Mm,Chi_20)
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VMADDSUBRDUP(7 *N,%r10,Mm,Chi_21)
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VMADDSUBRDUP(8 *N,%r10,Mm,Chi_22)
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VMADDSUBRDUP(9 *N,%r10,Mm,Chi_30)
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VMADDSUBRDUP(10*N,%r10,Mm,Chi_31)
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VMADDSUBRDUP(11*N,%r10,Mm,Chi_32)
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);
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}
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a0 = a0+incr;
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a1 = a1+incr;
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@ -672,13 +704,26 @@ void CayleyFermion5D<Impl>::MooeeInternalZAsm(const FermionField &psi, FermionFi
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}}
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{
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int lexa = s1+LLs*site;
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/*
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SiteSpinor tmp;
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asm (
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VSTORE(0,%0,Chi_00) VSTORE(1 ,%0,Chi_01) VSTORE(2 ,%0,Chi_02)
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VSTORE(3,%0,Chi_10) VSTORE(4 ,%0,Chi_11) VSTORE(5 ,%0,Chi_12)
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VSTORE(6,%0,Chi_20) VSTORE(7 ,%0,Chi_21) VSTORE(8 ,%0,Chi_22)
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VSTORE(9,%0,Chi_30) VSTORE(10,%0,Chi_31) VSTORE(11,%0,Chi_32)
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VSTORE(0,%0,pChi_00) VSTORE(1 ,%0,pChi_01) VSTORE(2 ,%0,pChi_02)
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VSTORE(3,%0,pChi_10) VSTORE(4 ,%0,pChi_11) VSTORE(5 ,%0,pChi_12)
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VSTORE(6,%0,pChi_20) VSTORE(7 ,%0,pChi_21) VSTORE(8 ,%0,pChi_22)
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VSTORE(9,%0,pChi_30) VSTORE(10,%0,pChi_31) VSTORE(11,%0,pChi_32)
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: : "r" ((uint64_t)&tmp) : "memory" );
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*/
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asm (
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VSTORE(0,%0,pChi_00) VSTORE(1 ,%0,pChi_01) VSTORE(2 ,%0,pChi_02)
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VSTORE(3,%0,pChi_10) VSTORE(4 ,%0,pChi_11) VSTORE(5 ,%0,pChi_12)
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VSTORE(6,%0,pChi_20) VSTORE(7 ,%0,pChi_21) VSTORE(8 ,%0,pChi_22)
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VSTORE(9,%0,pChi_30) VSTORE(10,%0,pChi_31) VSTORE(11,%0,pChi_32)
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: : "r" ((uint64_t)&chi[lexa]) : "memory" );
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// if ( 1 || (site==0) ) {
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// std::cout<<site << " s1 "<<s1<<"\n\t"<<tmp << "\n't" << chi[lexa] <<"\n\t"<<tmp-chi[lexa]<<std::endl;
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// }
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}
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}
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}
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