364793154b
Reverted checkerboard changes
2021-04-09 15:47:17 +01:00
3e2ae1e9af
Added profiling messages to pick and set checkerboard functions
2021-04-08 16:58:47 +01:00
Henrique Rocha
d38ae2fd18
Merge branch 'develop' of https://github.com/Heinrich-BR/Grid into develop
2021-04-06 17:18:39 +01:00
Henrique Rocha
030e7754e4
Merge remote-tracking branch 'upstream/develop' into develop
2021-04-06 17:16:13 +01:00
Peter Boyle
e2a0142d87
Merge pull request #348 from AndrewYongZhenNing/develop
...
Conserved Tadpole Implementation for Shamir Action Only
2021-04-06 10:49:00 -04:00
895244ecc3
Merge with upstream; implemented conserved tadpole for Shamir action.
2021-04-06 13:46:33 +01:00
addeb621a7
Implemented tadpole operator for Shamir action.
2021-04-06 13:45:37 +01:00
3b7fce1e76
Reverted checkerboard changes
2021-04-02 14:38:41 +01:00
4d15417f93
Merge remote-tracking branch 'upstream/develop' into develop
2021-04-01 18:28:15 +01:00
ab3c855f65
Merge branch 'develop' of https://github.com/Heinrich-BR/Grid into develop
2021-04-01 18:22:05 +01:00
92e2c517d8
Changed pick- and setCheckerboard to use accelerator_for
2021-04-01 18:21:19 +01:00
Peter Boyle
a7fb25adf6
Make Cshift fields static to avoid repeated reallocaate overhead
2021-03-29 21:44:14 +02:00
Peter Boyle
e947992957
Improved force terms
2021-03-29 20:04:06 +02:00
Peter Boyle
bb89a82a07
Staggered coalseced read
2021-03-29 20:01:15 +02:00
Christoph Lehner
2bb374daea
hip-friendly
2021-03-19 11:33:23 +01:00
Peter Boyle
8bdadbadac
Cold start
2021-03-18 15:41:14 -04:00
Peter Boyle
15c50a7442
Explicit instantiate the template function
2021-03-18 15:40:42 -04:00
Peter Boyle
49b0af2c95
Update of tests to compile with the sRNG addition.
...
Audited the code conventions (again) with the CPS momentum denominator
and added anti periodic in time to the Test_mobius_force.cc and
tested the Test_dwf_gpforce.
Promoted thesee to test full HMC hamiltonian, tr P^2/2 + phidag MdagM phi
with the same pdot and Udot as audited in the Integrator.h etc...
With full comments and sources for factors.
2021-03-18 09:10:02 -04:00
Peter Boyle
9c2b37218a
sRNG parameter added
2021-03-18 06:24:11 -04:00
Peter Boyle
3c67d626ba
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-12 15:36:55 +01:00
Peter Boyle
51f506553c
Read out the local ID once, and store
2021-03-12 15:33:04 +01:00
Peter Boyle
226be84937
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-12 09:31:50 -05:00
Peter Boyle
001814b442
updated to do list. Start adding DDHMC work items
2021-03-12 09:31:17 -05:00
Peter Boyle
db3ac67506
Update thread issue
2021-03-12 14:55:07 +01:00
Peter Boyle
da91a884ef
NVCC versions found buggy added as guard
2021-03-11 23:54:53 +01:00
Peter Boyle
a71e6755e3
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-11 22:43:06 +01:00
Peter Boyle
cd5891eecd
Test that fails on Cuda 11.0
2021-03-11 22:34:28 +01:00
Peter Boyle
5bb7336f27
Merge pull request #347 from pjgeorg/fix-autotools-avx512
...
Fix inconsistent SIMD option AVX512
Thanks
2021-03-11 16:29:07 -05:00
Peter Boyle
ce1fc1f48a
Possible fallback plan for Fionn's compiler bbug in nvcc
2021-03-11 22:20:53 +01:00
Peter Georg
82402c6a7c
Add simd option SKL for ICC
2021-03-11 13:08:40 +01:00
Peter Georg
d9c4afe5b7
Fix inconsistent configure option AVX512
...
Before this change AVX512 enabled different instruction sets depending
on the compiler:
For Intel C++ Compiler Classic (ICC):
AVX512F, AVX512CD, AVX512DQ, AVX512BW, AVX512VL
i.e. Intel Xeon Skylake and newer
For Intel ICX, gcc, clang:
AVX512F, AVX512CD, AVX512ER, AVX512PF
i.e. Intel Xeon Phi x200/x205 (KNL/KNM)
With this commit AVX512 now only enables the common instruction sets
supported by all CPUs supporting any AVX-512 instructions set:
AVX512F and AVX512CD (called COMMON-AVX512 by icc)
2021-03-11 12:58:49 +01:00
Peter Boyle
f786ff8d69
Extend test from Fionn, fails on A100 apparently
2021-03-10 14:32:06 -05:00
u61464
a651caed5f
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-10 06:23:51 -08:00
u61464
0e21adb3f6
Gives 200GF/s on SyCL/DG1 8^4, doesn't uglify develop for other platforms too badly.
...
Easy to revert to clean more C++ stylistic code. Theres a SYCL_HACK macro I will clean up later once dpcpp
evolves a central nervous systems.
2021-03-10 05:40:51 -08:00
Peter Boyle
58bf9b9e6d
Clean up test
2021-03-10 02:45:22 +01:00
Peter Boyle
2146eebb65
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-09 04:31:46 +01:00
Peter Boyle
6a429ee6d3
2d loop hits Nvidia 16bit limit on large local vols
2021-03-09 04:31:10 +01:00
Peter Boyle
4d1ea15c79
More verbosity. The 16bit limit on Grid.y, Grid.z is annoying
2021-03-09 04:29:37 +01:00
Peter Boyle
a76cb005e0
Update Tensor_exp.h
2021-03-08 13:37:57 -05:00
Christoph Lehner
49ecbc81d4
Merge pull request #24 from ThomasWurm/feature/gpt
...
Put GlobalSum outside the slice loop in sliceSum
2021-03-08 16:01:47 +01:00
Thomas Wurm
9e5fb52eb9
Put GlobalSum outside the slice loop
2021-03-08 13:53:34 +01:00
Peter Boyle
a9604367c1
Merge pull request #336 from lehner/feature/gpt
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Make ShmDims configurable; adjust GRID_MAX_SIMD to allow for 128 byte width on GPUs
2021-03-05 13:17:19 -05:00
Peter Boyle
d7065023cc
Merge pull request #332 from mmphys/feature/mres_schur
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Optional changes to Test_cayley_mres e.g. Schur solver
2021-03-05 12:47:07 -05:00
Peter Boyle
89d299ceec
Merge pull request #333 from mmphys/bugfix/LatTransfer
...
Fix convertType for GPU in Lattice_transfer.h
2021-03-05 12:46:33 -05:00
Peter Boyle
e34eda66df
Merge pull request #344 from felixerben/feature/XiToSigma
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Feature/xi to sigma
2021-03-05 12:45:44 -05:00
Christoph Lehner
b24181aa4f
Update Coordinate.h
...
Revert GRID_MAX_SIMD change
2021-03-05 16:56:58 +01:00
Peter Boyle
aa173e2998
Update README.md
2021-03-05 10:25:33 -05:00
7a19432e0b
whitespace
2021-03-05 10:57:09 +00:00
9b15704290
tested and consitent
2021-03-05 10:42:32 +00:00
Michael Marshall
017f955b2d
Merge branch 'develop' into feature/mres_schur
...
* develop:
Pass serial RNG around
Sycl happier
2021-03-04 20:42:02 +00:00
