Peter Boyle
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0d80eeb545
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small DDHMC update
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2022-03-03 16:56:02 -05:00 |
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Peter Boyle
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b0f4eee78b
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New files
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2022-03-01 19:09:13 -05:00 |
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Peter Boyle
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5340e50427
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HMC running with new formulation
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2022-03-01 17:10:25 -05:00 |
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Peter Boyle
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0f1c5b08a1
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Dirichlet filters running on AMD and now integrated in Fermion op
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2022-02-23 19:29:28 -05:00 |
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Peter Boyle
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aab3bcb46f
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Dirichlet first cut - wrong answers on dagger multiply.
Struggling to get a compute node so changing systems
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2022-02-22 19:58:33 +00:00 |
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Peter Boyle
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c322420580
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Dont instantiate an Nc=3 and non-GP hardwired code for other implementations
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2022-02-14 16:04:08 +00:00 |
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Daniel Richtmann
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1b6b12589f
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Get splitting up into implementation and instantiation files correct
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2022-02-02 00:51:11 +01:00 |
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Daniel Richtmann
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3082ab8252
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Check in compact version of wilson clover fermions
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2022-02-02 00:50:05 +01:00 |
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Daniel Richtmann
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add86cd7f4
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Abandon ET for clover application, use construct similar to multLink
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2022-02-01 23:09:06 +01:00 |
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Daniel Richtmann
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0b6fd20c54
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Enable memory coalescing in clover term generation
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2022-02-01 23:09:06 +01:00 |
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Daniel Richtmann
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e83423fee6
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Refactor clover to align with other files and prepare for upcoming changes
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2022-02-01 23:09:06 +01:00 |
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Peter Boyle
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195ab2888d
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Merge branch 'develop' into develop
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2021-10-27 20:26:57 -04:00 |
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Peter Boyle
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ba7e371b90
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Warning free compile on Tursa.
Hopefully got all reqd virtual dtors
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2021-10-21 19:56:52 +01:00 |
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a976fa6746
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expose gauge group in GImpl and generic Nc fix
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2021-10-05 14:19:47 +01:00 |
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Luchang Jin
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4b24800132
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AVX512 drop mixed precision as well
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2021-09-15 16:29:47 -04:00 |
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Christoph Lehner
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3d0f88e702
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A64FX drop mixed precision as well
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2021-09-15 18:38:32 +02:00 |
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Peter Boyle
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86e33c8ab2
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Significant GPU perf speed up finished
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2021-09-14 16:14:23 +01:00 |
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Peter Boyle
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a7b943b33e
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Remove half prec comms
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2021-09-14 05:05:33 +01:00 |
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Peter Boyle
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7440cde92f
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No half prec comms; coalesced access on GPU
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2021-09-14 05:04:56 +01:00 |
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Peter Boyle
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4c88104a73
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Fix compile warns
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2021-09-11 23:08:05 +01:00 |
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Peter Boyle
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73b944c152
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Drop half prec comms for now.
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2021-09-11 23:07:18 +01:00 |
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Peter Boyle
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d1b0b7f5c6
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Half prec comms dropping
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2021-09-11 23:05:40 +01:00 |
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Peter Boyle
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381d8797d0
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Drop half prec comms for now
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2021-09-11 23:05:02 +01:00 |
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Andrew Yong
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770680669d
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Whitespace removal.
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2021-08-04 09:21:59 +01:00 |
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Andrew Yong
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0cdfc5cf22
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Merge remote-tracking branch 'upstream/develop' into develop
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2021-07-30 14:40:55 +01:00 |
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u61464
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8cfc7342cd
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staggered hand unroll read coalesce
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2021-05-05 14:17:18 -07:00 |
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54c6b1376d
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Quick fix of conserved current implementation in CayleyFermion5D. Now function treats current insertion with appropriate periodic boundary conditions in the mu=3 direction.
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2021-04-21 16:56:46 +01:00 |
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f3f11b586f
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Tadpole sign now in front of forward hopping term to be consistent with previous implementation and analytic form.
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2021-04-17 12:44:27 +01:00 |
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8083e3f7e8
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Sign factor for tadpole implementation corrected.
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2021-04-15 11:14:31 +01:00 |
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895244ecc3
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Merge with upstream; implemented conserved tadpole for Shamir action.
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2021-04-06 13:46:33 +01:00 |
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addeb621a7
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Implemented tadpole operator for Shamir action.
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2021-04-06 13:45:37 +01:00 |
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Peter Boyle
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bb89a82a07
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Staggered coalseced read
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2021-03-29 20:01:15 +02:00 |
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Peter Boyle
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51f506553c
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Read out the local ID once, and store
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2021-03-12 15:33:04 +01:00 |
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u61464
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0e21adb3f6
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Gives 200GF/s on SyCL/DG1 8^4, doesn't uglify develop for other platforms too badly.
Easy to revert to clean more C++ stylistic code. Theres a SYCL_HACK macro I will clean up later once dpcpp
evolves a central nervous systems.
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2021-03-10 05:40:51 -08:00 |
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Peter Boyle
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a9604367c1
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Merge pull request #336 from lehner/feature/gpt
Make ShmDims configurable; adjust GRID_MAX_SIMD to allow for 128 byte width on GPUs
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2021-03-05 13:17:19 -05:00 |
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Peter Boyle
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c90beee774
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Merge branch 'develop' of https://github.com/paboyle/Grid into develop
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2021-03-03 23:50:29 +01:00 |
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Peter Boyle
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1eea9d73b9
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Pass serial RNG around
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2021-03-03 23:50:01 +01:00 |
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u61464
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679d1d22f7
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Sycl happier
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2021-03-03 11:21:43 -08:00 |
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Peter Boyle
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442336bd96
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Hand unrolled to use optimised code paths on GPU for coalesced reads in Wilson case.
Other cases to do. This now includes comms code path.
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2021-03-02 14:50:51 +01:00 |
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Christoph Lehner
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9c9566b9c9
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Merge pull request #23 from paboyle/develop
Sync
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2021-03-01 12:33:51 +01:00 |
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Daniel Richtmann
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e3d019bc2f
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Enable performance counting in WilsonFermion like in others
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2021-02-22 15:25:40 +01:00 |
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Peter Boyle
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eda9ab487b
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MADWF 5d source option for hadrons - look at Grid of source
Abort on GPU error
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2021-02-08 10:47:22 -05:00 |
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Peter Boyle
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69f1f04f74
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Merge branch 'develop' of https://github.com/paboyle/Grid into develop
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2021-01-21 21:39:59 -05:00 |
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Peter Boyle
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ff1fa98808
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Fix for GPU conserveed current
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2021-01-21 21:38:23 -05:00 |
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Peter Boyle
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99445673f6
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Gparity fix, and plaquette IO
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2021-01-14 21:00:36 -05:00 |
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Christoph Lehner
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299d0de066
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Merge pull request #21 from paboyle/develop
Sync
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2020-12-22 20:59:15 +01:00 |
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Nils Meyer
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45d49d8648
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clean up
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2020-12-19 03:35:18 +01:00 |
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Nils Meyer
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3f9ae6e7e7
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Merge branch 'develop' into feature/a64fx-3
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2020-12-19 02:37:11 +01:00 |
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Nils Meyer
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4dd9e39e0d
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up to +36% performance gain for dslash/dwf on QPACE 4 using GCC 10.1.1
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2020-12-19 00:54:31 +01:00 |
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Michael Marshall
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873519e960
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Enable existing conserved current code for CUDA (compiles OK for CUDA 10.1). Add option to Test_cayley_mres to load a configuration
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2020-12-14 16:06:10 +00:00 |
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