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Author SHA1 Message Date
Peter Boyle c5e081d69c Re-Merge branch 'develop' into feature/gpu-port 
Pull in Regensburg MultiGrid pull request
 2019-01-03 01:50:16 +00:00
Peter Boyle 535a6aaf05 Update todo list 2019-01-02 22:07:51 +00:00
Peter Boyle 91a7fe247b Merge branch 'DanielRichtmann-feature/wilsonmg' into develop 2019-01-02 14:40:31 +00:00
Peter Boyle 8a1be021d3 Merge branch 'feature/wilsonmg' of https://github.com/DanielRichtmann/Grid into DanielRichtmann-feature/wilsonmg 2019-01-02 14:39:59 +00:00
Peter Boyle e73b909a48 Make tests running past nvcc. Different NVCC versions proving tricky to keep happy. This is 9.2 2019-01-02 12:05:30 +00:00
Peter Boyle a4d9200293 Fixing AVX 512 instantiation error. Need to move to extern templates urgently. 2019-01-02 00:27:07 +00:00
Peter Boyle 350508bdb3 pugixml problem 2019-01-01 16:38:54 +00:00
Peter Boyle 38852737e4 No compile fix on clang 2019-01-01 15:55:13 +00:00
Peter Boyle 802404c78c Remove warnings under NVCC and move parallel_for to thread-loop 2019-01-01 15:08:09 +00:00
Peter Boyle 0e9b591c1c NVCC warning suppression 2019-01-01 15:07:47 +00:00
Peter Boyle c43a2b599a GPU support 2019-01-01 15:07:29 +00:00
Peter Boyle 8c91e82ee8 GPU clean up, remove parallel_for. Split into accelerator_loop, thread_loop 
cases, and collides with parallel_for in thrust
 2019-01-01 15:06:46 +00:00
Peter Boyle 9d866d062a GPU support improvements 2019-01-01 15:05:03 +00:00
Peter Boyle 3a4e397e72 Deprecating JSON, too hard to support under NVCC 2019-01-01 15:04:33 +00:00
Peter Boyle 2b6cfe555f Disable JSON on NVCC. Maybe unsupport JSON full stop. XML and JSON is too many formats in my view. 2019-01-01 15:03:50 +00:00
Peter Boyle 7df58dd883 Photon syntax gave problems with NVCC 2019-01-01 15:03:29 +00:00
Peter Boyle 4bf86ae60a NVCC clean up 2019-01-01 15:02:50 +00:00
Peter Boyle 07ee87ff5a GPU happy. Still need to prevent hand kernels being callable under NVCC 2019-01-01 15:00:33 +00:00
Peter Boyle 0c2498fe2f Explicit instantiation needed for NVCC 2019-01-01 13:55:12 +00:00
Peter Boyle ad2e65dad5 GPU related updates 2019-01-01 13:54:40 +00:00
Peter Boyle 715babeac8 GPU reductions first cut; use thrust, non-reproducible. Inclusive scan can fix this if desired. 
Local reduction to LatticeComplex and then further reduction.
 2019-01-01 13:53:37 +00:00
Peter Boyle 3eae9a9e3f update NVCC flags 2019-01-01 13:49:15 +00:00
Peter Boyle 186aad065f Roll forward Eigen in attempt to make CUDA happy 2019-01-01 13:48:32 +00:00
Peter Boyle bf5685eb11 Update todo list 2019-01-01 13:48:06 +00:00
Peter Boyle 4a96c067ae Remove warnings from NVCC 2019-01-01 13:43:09 +00:00
Peter Boyle ab063f33c0 Offload the linear combinations in CG 2019-01-01 13:42:13 +00:00
Peter Boyle 9efcc535bc Cleaner drop from CUDA mode around Eigen includes. Remains difficult to let Eigen compile under nvcc with version issues. 2019-01-01 13:39:10 +00:00
Peter Boyle 231b61d012 std::array by default 2019-01-01 13:37:35 +00:00
Peter Boyle e898f4f0b0 Whitespace 2019-01-01 13:36:55 +00:00
Peter Boyle d5db5f5242 Wrong dimension used in a temporary 2018-12-20 10:49:45 +00:00
Peter Boyle 2fcedb13dd Step size modification in HMC; ICC happy thread pragmas 2018-12-20 09:32:33 +00:00
Peter Boyle 35ed1defac Passes make check now single and double compile 2018-12-19 11:09:32 +00:00
Peter Boyle 4e95accf80 Namespace fix 2018-12-15 21:46:17 +00:00
Peter Boyle 422764757d Updates in tests to make all of Grid compile 2018-12-14 16:55:54 +00:00
Peter Boyle afc462bd58 Bracketing issue in macro 2018-12-13 10:53:22 +00:00
Peter Boyle b57a4d32aa Merge branch 'develop' into feature/gpu-port 2018-12-13 05:11:34 +00:00
Peter Boyle 33a0bbb17b Const correctness 2018-11-19 11:27:57 +00:00
Peter Boyle f3f24b3017 Optional Twisted BC's added, in "DoubleStore" for WilsonImpl. 
Untested but doesn't affect answers when twists are all zero. The zero is the default behaviour
for ImplParams.
 2018-11-08 12:55:25 +00:00
Peter Boyle 68c13045d6 Added a test for Felix and Michael to look at 2018-11-07 23:40:15 +00:00
Peter Boyle e9b6f58fdc Allow shrinking machine in orthog direction for extract slice local 2018-11-07 23:39:18 +00:00
Peter Boyle 839605c45c Verbose reduce 2018-11-07 23:38:46 +00:00
Peter Boyle 2205b1e63e Add CXX to grid-config 2018-11-07 13:32:46 +00:00
Peter Boyle 6f421c7a6f Block solver in the SchurRedBlack plus timing report cleaner 2018-11-07 12:26:56 +00:00
Peter Boyle b62b9ac214 Patch to broken assertion 2018-11-06 22:18:17 +00:00
Peter Boyle 8c3a599148 Block solver test 2018-11-06 16:44:58 +00:00
Peter Boyle 24c07694bc Mixed precision now supported in MADWF 2018-10-14 00:22:52 +01:00
Peter Boyle f0229025e2 MADWF working across a range of actions 2018-10-13 19:55:03 +01:00
Peter Boyle 6de9a45a09 NPR first cut by Julia Kettle 2018-10-12 11:00:58 +01:00
Peter Boyle 03c3d495a2 First cut (non functional NPR code) developed by Julia Kettle 2018-10-12 10:59:33 +01:00
Peter Boyle 49f25e08e8 PauliVillars based 4D -> 5D reconstruction with Fourier Accelerated PV inverse 
by Christoph. Differs from the one by Rudy in BFM since it vectorises the twisted
4D solves in pairs.
 2018-10-11 12:35:32 +01:00
paboyle 8bab544c2f Updated manual pdf 2018-09-20 18:51:11 +01:00
paboyle 76fc06a5dc Updates with todo from Carleton 2018-09-20 18:50:11 +01:00
Peter Boyle adbdc4e65b Half comms not working on GPU yet, so disable. 2018-09-11 05:15:22 +01:00
Peter Boyle e4deea4b94 Weird bug appears with Vector<Vector<>>. 
"fix" with std::vector<Vector<>>

Lies in the face table code. But think there is some latent problem.
Possibly in my allocator since it is caching, but could simplify or eliminate the caching
option and retest. One to look at later.
 2018-09-11 04:36:57 +01:00
Peter Boyle 94d721a20b Comments on further topology discovery work 2018-09-11 04:20:04 +01:00
Peter Boyle 7bf82f5b37 Offload the face handling to GPU 2018-09-10 11:28:42 +01:00
Peter Boyle f02c7ea534 Peer to peer on GPU's setup 2018-09-10 11:26:20 +01:00
Peter Boyle bc503b60e6 Offloadable gather code 2018-09-10 11:21:25 +01:00
Peter Boyle 704ca162c1 Offloadable compression 2018-09-10 11:20:50 +01:00
Peter Boyle b5329d8852 Protect against zero length loops giving a kernel call failure 2018-09-10 11:20:07 +01:00
Peter Boyle f27b9347ff Better unquiesce MPI coverage 2018-09-10 11:19:39 +01:00
Peter Boyle b4967f0231 Verbose and error trapping cleaner 2018-09-09 14:28:02 +01:00
Peter Boyle 6d0f1aabb1 Fix the multi-node path 2018-09-09 14:27:37 +01:00
Peter Boyle f4bfeb835d Drop back to smaller Ls 2018-09-09 14:25:06 +01:00
Peter Boyle 394b7b6276 Verbose decrease 2018-09-09 14:24:46 +01:00
paboyle c7c9072313 Documentation 2018-09-06 16:01:42 +01:00
paboyle 27cdb79063 Sha used to seed from a unique string 2018-08-10 15:11:01 +01:00
Peter Boyle 3791a38f7c Optimised the MesonField a bit more 2018-08-01 08:27:27 +01:00
Peter Boyle 142f7b0c86 Updated the A2A Meson Field module 2018-07-31 15:58:02 +01:00
Peter Boyle 60c43151c5 Merge branch 'feature/hadrons-a2a' of https://github.com/paboyle/Grid into feature/hadrons-a2a 2018-07-31 01:09:02 +01:00
paboyle e036800261 Eigen fix 2018-07-31 01:08:42 +01:00
Peter Boyle 62900def36 Merge branch 'feature/hadrons-a2a' of https://github.com/paboyle/Grid into feature/hadrons-a2a 2018-07-31 00:36:26 +01:00
paboyle e3a309a73f Eigen happiness 2018-07-31 00:35:17 +01:00
Peter Boyle 00b92a91b5 Optimising 2018-07-28 23:46:22 +01:00
paboyle 65533741f7 7 moms 2018-07-28 16:17:47 +01:00
paboyle 44f4f5c8e2 Momentum loop 2018-07-27 23:00:16 +01:00
paboyle 71e1006ba8 Updated meson field benchmark for dirac structures 2018-07-26 09:09:29 +01:00
Peter Boyle da17a015c7 Pack the stencil smaller for 128 bit access 2018-07-23 06:12:45 -04:00
Peter Boyle 1fd08c21ac make simd width configure time option for GPU 2018-07-23 06:10:55 -04:00
Peter Boyle 28db0631ff Hack to force 128bit accesses 2018-07-23 06:10:27 -04:00
Peter Boyle b35401b86b Fix CUDA_ARCH. Need to simplify. See when new eigen release happens 2018-07-23 06:09:33 -04:00
Peter Boyle a0714de8ec Define vector length for GPU 2018-07-23 06:09:05 -04:00
Peter Boyle 21a1710b43 Verbose vector length 2018-07-23 06:08:39 -04:00
Peter Boyle b2b5137d28 Finally starting to get decent performance on Volta 2018-07-13 12:06:18 -04:00
paboyle ec9939c1ba Test for faster implementation of meson field inner loop 
This should be possible to cache block at outer levels, global sum across nodes not performed
and deferred to caller to block them all into a big all reduce.
Nc=3 and Fermion is hard coded in an ugly way. We might think about benchmarking whether
a product without the conjugate should be made available by Grid.

It is not clear whether the explicit unroll, or the performing of conjugate on left once
was the real source of the speed up.

Gives 70-80 GF/s on my laptop (single) half that double, and 70GB/s to cache.

This is competitive with dslash and a reasonable stopping point for the optimisation. If necessary we can revisit.
 2018-07-10 12:38:51 +01:00
Peter Boyle 2cc07450f4 Fastest option for the dslash 2018-07-05 09:57:55 -04:00
Peter Boyle c0e8bc9da9 Current version gets 250 - 320 GF/s on Volta on the target 12^4 volume. 2018-07-05 07:10:25 -04:00
Peter Boyle b1265ae867 Prettify code 2018-07-05 07:08:06 -04:00
Peter Boyle 32bb85ea4c Standard extractLane is fast 2018-07-05 07:07:30 -04:00
Peter Boyle ca0607b6ef Clearer kernel call meaning 2018-07-05 07:06:15 -04:00
Peter Boyle 19b527e83f Better extract merge for GPU. Let the SIMD header files define the pointer type for 
access. GPU redirects through builtin float2, double2 for complex
 2018-07-05 07:05:13 -04:00
Peter Boyle 4730d4692a Fast lane extract, saturates bandwidth on Volta for SU3 benchmarks 2018-07-05 07:03:33 -04:00
Peter Boyle 1bb456c0c5 Minor GPU vector width change 2018-07-05 07:02:04 -04:00
Peter Boyle 4b04ae3611 Printing improvement 2018-07-05 06:59:38 -04:00
Peter Boyle 2f776d51c6 Gpu specific benchmark saturates memory. Can enhance Grid to do this for expressions, 
but a bitof (known) work.
 2018-07-05 06:58:37 -04:00
paboyle 3a50afe7e7 GPU dslash updates 2018-06-27 22:32:21 +01:00
paboyle f8e880b445 Loop for s and xyzt offlow 2018-06-27 21:49:57 +01:00
paboyle 3e947527cb Move looping over "s" and "site" into kernels for GPU optimisatoin 2018-06-27 21:29:43 +01:00
paboyle 31f65beac8 Move site and Ls looping into the kernels 2018-06-27 21:28:48 +01:00
paboyle 38e2a32ac9 Single SIMD lane operations for CUDA 2018-06-27 21:28:06 +01:00