ef0ddd5d04
std::vector serialisation in hdf5 uses a different format if the vector is ragged. When reading back std::vector we need to check which format we're reading (since we don't know a priori) and this involves looking for attributes that may not exist. The c++ API: a) throws; and b) prints voluminous logging. Switched to non-throwing, non-logging, C version of the API after code review.
2021-05-24 18:43:55 +01:00
9b73dacf50
First row might still be ragged if multi dimensional. attrExists() doesn't throw, but easier to wrap in try ... catch than to explain in comment.
2021-05-22 04:34:32 +01:00
244b4aa07f
Serialise std::vector of numeric types as multidimensional object if size is regular ... or individually if ragged
2021-05-21 20:08:56 +01:00
8cfc7342cd
staggered hand unroll read coalesce
2021-05-05 14:17:18 -07:00
15ae317858
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-05-04 08:40:38 -07:00
834f536b5f
Fastest option on SyCL is now std::complex
2021-05-04 08:40:18 -07:00
c332d9f08b
Merge pull request #356 from felixerben/bugfix/stoutSmearing
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Jamie's fix
2021-04-27 14:10:49 -04:00
cf2923d5dd
Jamie's fix
2021-04-27 16:53:37 +01:00
0e4413ddde
Merge pull request #355 from felixerben/bugfix/stoutSmearing
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bugfix 3D stout smearing
2021-04-27 08:01:55 -04:00
009ccd581e
bugfix 3D stout smearing
2021-04-26 10:36:33 +01:00
8cd4263974
Tests compile
2021-04-25 22:20:37 -04:00
d45c868656
Change interface
2021-04-25 10:53:34 -04:00
955a8113de
Expose label only to reduce number of parameters
2021-04-25 10:36:38 -04:00
dbe210dd53
Open the ens_id
2021-04-25 10:25:59 -04:00
86e11743ca
set twists
2021-04-20 10:19:11 -04:00
980e721f6e
Update MetaData.h
2021-04-13 09:33:01 -04:00
e2a0142d87
Merge pull request #348 from AndrewYongZhenNing/develop
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Conserved Tadpole Implementation for Shamir Action Only
2021-04-06 10:49:00 -04:00
895244ecc3
Merge with upstream; implemented conserved tadpole for Shamir action.
2021-04-06 13:46:33 +01:00
addeb621a7
Implemented tadpole operator for Shamir action.
2021-04-06 13:45:37 +01:00
a7fb25adf6
Make Cshift fields static to avoid repeated reallocaate overhead
2021-03-29 21:44:14 +02:00
e947992957
Improved force terms
2021-03-29 20:04:06 +02:00
bb89a82a07
Staggered coalseced read
2021-03-29 20:01:15 +02:00
8bdadbadac
Cold start
2021-03-18 15:41:14 -04:00
15c50a7442
Explicit instantiate the template function
2021-03-18 15:40:42 -04:00
49b0af2c95
Update of tests to compile with the sRNG addition.
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Audited the code conventions (again) with the CPS momentum denominator
and added anti periodic in time to the Test_mobius_force.cc and
tested the Test_dwf_gpforce.
Promoted thesee to test full HMC hamiltonian, tr P^2/2 + phidag MdagM phi
with the same pdot and Udot as audited in the Integrator.h etc...
With full comments and sources for factors.
2021-03-18 09:10:02 -04:00
9c2b37218a
sRNG parameter added
2021-03-18 06:24:11 -04:00
3c67d626ba
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-12 15:36:55 +01:00
51f506553c
Read out the local ID once, and store
2021-03-12 15:33:04 +01:00
226be84937
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-12 09:31:50 -05:00
001814b442
updated to do list. Start adding DDHMC work items
2021-03-12 09:31:17 -05:00
db3ac67506
Update thread issue
2021-03-12 14:55:07 +01:00
da91a884ef
NVCC versions found buggy added as guard
2021-03-11 23:54:53 +01:00
a71e6755e3
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-11 22:43:06 +01:00
cd5891eecd
Test that fails on Cuda 11.0
2021-03-11 22:34:28 +01:00
5bb7336f27
Merge pull request #347 from pjgeorg/fix-autotools-avx512
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Fix inconsistent SIMD option AVX512
Thanks
2021-03-11 16:29:07 -05:00
ce1fc1f48a
Possible fallback plan for Fionn's compiler bbug in nvcc
2021-03-11 22:20:53 +01:00
82402c6a7c
Add simd option SKL for ICC
2021-03-11 13:08:40 +01:00
d9c4afe5b7
Fix inconsistent configure option AVX512
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Before this change AVX512 enabled different instruction sets depending
on the compiler:
For Intel C++ Compiler Classic (ICC):
AVX512F, AVX512CD, AVX512DQ, AVX512BW, AVX512VL
i.e. Intel Xeon Skylake and newer
For Intel ICX, gcc, clang:
AVX512F, AVX512CD, AVX512ER, AVX512PF
i.e. Intel Xeon Phi x200/x205 (KNL/KNM)
With this commit AVX512 now only enables the common instruction sets
supported by all CPUs supporting any AVX-512 instructions set:
AVX512F and AVX512CD (called COMMON-AVX512 by icc)
2021-03-11 12:58:49 +01:00
f786ff8d69
Extend test from Fionn, fails on A100 apparently
2021-03-10 14:32:06 -05:00
a651caed5f
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-10 06:23:51 -08:00
0e21adb3f6
Gives 200GF/s on SyCL/DG1 8^4, doesn't uglify develop for other platforms too badly.
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Easy to revert to clean more C++ stylistic code. Theres a SYCL_HACK macro I will clean up later once dpcpp
evolves a central nervous systems.
2021-03-10 05:40:51 -08:00
58bf9b9e6d
Clean up test
2021-03-10 02:45:22 +01:00
2146eebb65
Merge branch 'develop' of https://github.com/paboyle/Grid into develop
2021-03-09 04:31:46 +01:00
6a429ee6d3
2d loop hits Nvidia 16bit limit on large local vols
2021-03-09 04:31:10 +01:00
4d1ea15c79
More verbosity. The 16bit limit on Grid.y, Grid.z is annoying
2021-03-09 04:29:37 +01:00
a76cb005e0
Update Tensor_exp.h
2021-03-08 13:37:57 -05:00
a9604367c1
Merge pull request #336 from lehner/feature/gpt
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Make ShmDims configurable; adjust GRID_MAX_SIMD to allow for 128 byte width on GPUs
2021-03-05 13:17:19 -05:00
d7065023cc
Merge pull request #332 from mmphys/feature/mres_schur
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Optional changes to Test_cayley_mres e.g. Schur solver
2021-03-05 12:47:07 -05:00
89d299ceec
Merge pull request #333 from mmphys/bugfix/LatTransfer
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Fix convertType for GPU in Lattice_transfer.h
2021-03-05 12:46:33 -05:00
e34eda66df
Merge pull request #344 from felixerben/feature/XiToSigma
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Feature/xi to sigma
2021-03-05 12:45:44 -05:00
