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Author SHA1 Message Date
Peter Boyle 95a8e4be64 rocblas 2023-12-20 21:27:59 -05:00
Peter Boyle abcd6b8cb6 Faster version 2023-12-19 15:17:46 -05:00
Peter Boyle e8f21c9b6d Memmory verbose control improvement 2023-12-19 15:16:58 -05:00
Peter Boyle e054078b11 Verbose 2023-12-05 16:15:17 -05:00
Peter Boyle 6835a7f208 Better logging, test on 81 point stencil 2023-11-29 19:20:47 -05:00
Peter Boyle f59993b979 Nbasis§ 2023-11-29 09:47:36 -05:00
Peter Boyle 2290b8f680 Verbose 2023-11-29 09:47:04 -05:00
Peter Boyle 2c54be651c Further updates 2023-11-29 09:43:29 -05:00
Peter Boyle e859a199df Reduce volume to interior for coarse stencil -- worth up to 4x gain 2023-11-28 10:23:16 -05:00
Peter Boyle 0a3682ad0b MultiRHS work 2023-11-28 07:43:37 -05:00
Peter Boyle 59abaeb5cd Time stamp 2023-11-24 12:56:45 -05:00
Peter Boyle 3e448435d3 Restrict to interior 2023-11-23 18:23:29 -05:00
Peter Boyle a294bc3c5b Relax constraints for multiRHS 2023-11-23 18:20:42 -05:00
Peter Boyle b302ad3d49 multiRHS test in place, passes Yay! 2023-11-23 18:20:15 -05:00
Peter Boyle 82fc4b1e94 Finalise 2023-11-23 18:19:41 -05:00
Peter Boyle b4f1740380 Finalise message 2023-11-23 18:19:16 -05:00
Peter Boyle 031f85247c multRHS initial support -- needs optimisation for multi project/promote. 
Bug fix in freeing intermediate grids to stop double free
 2023-11-23 18:18:35 -05:00
Peter Boyle 639cc6f73a better support for multiRHS coarse space 
Still to add restriction of domain of last loop to interior of padded cell (expect about 4.5x on test volume on Crusher)
 2023-11-23 18:16:26 -05:00
Peter Boyle 09946cf1ba Improved, works on 48^3 moving to multiRHS optimisations 2023-11-15 18:03:05 -05:00
Peter Boyle f4fa95e7cb Use 5.3.0 2023-11-15 18:01:38 -05:00
Peter Boyle 100e29e35e Allow expression as argument to norm2 2023-11-15 18:00:44 -05:00
Peter Boyle 4cbe471a83 devVector 2023-11-15 18:00:07 -05:00
Peter Boyle 8bece1f861 Faster to transpose the matrix and apply with column major order 2023-11-15 17:58:38 -05:00
Peter Boyle a3ca71ec01 Lots more setup options, still working on them 2023-11-15 17:58:04 -05:00
Peter Boyle e0543e8af5 Implement flexible preconditioned CG 2023-11-15 17:57:39 -05:00
Peter Boyle c1eb80d01a Print which have converged 2023-11-15 17:57:08 -05:00
Peter Boyle a26121d97b Better printing 2023-11-15 17:56:45 -05:00
Peter Boyle 043031a757 Report resid on failed convergence 2023-11-15 17:56:22 -05:00
Peter Boyle 807aeebe4c Resize tol in constructor 2023-11-15 17:55:57 -05:00
Peter Boyle 8aa1a37aad For Mirs preconditioner solver 2023-11-15 17:55:32 -05:00
Peter Boyle 4efa042f50 C++17 change 2023-10-24 10:57:50 -04:00
Peter Boyle c7cb37e970 c++17 accepted 2023-10-24 10:57:24 -04:00
Peter Boyle d34b207eab Avoid HIP warnings 2023-10-24 10:57:04 -04:00
Peter Boyle 0e6fa6f6b8 DOn't need the Cshift for the period optimisation 2023-10-24 10:56:31 -04:00
Peter Boyle 38b87de53f This works around a stacksize limit on AMD GPU 2023-10-24 10:56:07 -04:00
Peter Boyle aa5047a9e4 Faster blockProject blockPromote 2023-10-24 10:49:55 -04:00
Peter Boyle 24b6ee0df9 M4 file 2023-10-24 10:36:48 -04:00
Peter Boyle 1e79cc9cbe Avoid compiler error 2023-10-24 10:36:09 -04:00
Peter Boyle b3925df9c3 Verbose on CPU-GPU xfer, remove performance by default 2023-10-24 10:25:01 -04:00
Peter Boyle 351795ac3a Better messaging 2023-10-20 19:33:04 -04:00
Peter Boyle 9c9c42d0df Tests on frontier with real speed up . 3.5x on 16^3 at mq=0.01 2023-10-20 19:27:13 -04:00
Peter Boyle b6ad1bafc7 Normal memory SendToRecvFrom asynchronous for use in general stencil 
code
 2023-10-20 19:27:13 -04:00
Peter Boyle a5ca40f446 Better verbose -- track CPU GPU motion under --log Memory, others go to 
debug output stream
 2023-10-20 19:27:13 -04:00
Peter Boyle 9ab54c5565 Overlap comms & data copy/buffer assembly in Ghost zone exchange 2023-10-20 19:27:13 -04:00
Peter Boyle 4341d96bde Massively sped up coarse grid mult, comms 
Save 3ms spend (60% of time !) on cudaMalloc !!
 2023-10-20 19:27:13 -04:00
Peter Boyle 5fac47a26d Faster halo exchange 2023-10-20 19:27:13 -04:00
Peter Boyle e064f17346 Faster halo exchange 2023-10-20 19:27:13 -04:00
Peter Boyle afe10ba2a2 More digits 2023-10-20 19:27:13 -04:00
Peter Boyle 7cc3435ba8 Imporved General coarsened matrix 2023-10-20 19:27:13 -04:00
Peter Boyle 541772313c Verbosity 2023-10-20 19:27:13 -04:00
Peter Boyle 3747494a09 Notify delet public 2023-10-20 19:27:13 -04:00
Peter Boyle f2b98d0dcc Const safety 2023-10-20 19:27:13 -04:00
Peter Boyle 80471bf762 Alternate implementation involving face operations 2023-10-20 19:27:13 -04:00
Peter Boyle a06f63c110 Improved I/O and non-lexico option exposed to SciDAC format 2023-10-20 19:27:13 -04:00
Peter Boyle 0ae4478cd9 Checkpoint the subspace and ldop 2023-10-20 19:27:13 -04:00
Peter Boyle ae4e705e09 Use random vec as easier for debug 2023-10-20 19:27:13 -04:00
Peter Boyle f5dcea9dbf Updates for Frontier 2023-10-20 19:27:12 -04:00
Peter Boyle 2207309f8a Spack rules 2023-10-16 18:38:24 -04:00
Peter Boyle 2111e7ab5f Run at physical mass 2023-10-06 21:20:21 -04:00
Peter Boyle d29abfdcaf Transfer code to Frontier now 2023-10-06 21:03:34 -04:00
Peter Boyle a751c42cc5 Checkpoint restore the setup 2023-10-06 21:03:08 -04:00
Peter Boyle 6a3bc9865e Verbose change 2023-10-06 21:02:04 -04:00
Peter Boyle 4d5f7e4377 Verbose change 2023-10-06 21:01:37 -04:00
Peter Boyle 78b117fb78 Comment fix 2023-10-06 21:01:15 -04:00
Peter Boyle ded63a1319 Verbose change/pretty print 2023-10-06 21:00:53 -04:00
Peter Boyle df3e4d1e9c Return fix 2023-10-06 21:00:21 -04:00
Peter Boyle b58fd80379 I/O for coarse op and reorganise multigrid headers 2023-10-06 13:43:46 -04:00
Peter Boyle 7f6e0f57d0 No IO in file 2023-10-06 13:39:53 -04:00
Peter Boyle cae27678d8 gpermute 2023-10-06 13:39:19 -04:00
Peter Boyle 48ff655bad Slightly less verbose 2023-10-06 10:47:52 -04:00
Peter Boyle 2525ad4623 Slight clean up 2023-10-06 10:47:32 -04:00
Peter Boyle e7020017c5 Reorganise multigrid 2023-10-06 10:47:12 -04:00
Peter Boyle eacebfad74 Reorganise multigrid into multiple headers 2023-10-06 10:46:21 -04:00
Peter Boyle 3bc2da5321 Merge branch 'feature/scidac-wp1' of https://github.com/paboyle/Grid into feature/scidac-wp1 2023-10-05 16:57:59 -04:00
Peter Boyle 2d710d6bfd Optimised parameters for 16^3 2023-10-05 16:56:55 -04:00
Peter Boyle 6532b7f32b Eliminate older inefficient coarsening implementation 2023-10-05 16:56:15 -04:00
Peter Boyle 7b41b92d99 Only need to bad non-local dimensions 2023-10-05 16:55:48 -04:00
Peter Boyle dd557af84b ADEF1 and ADEF2 2 level CG 2023-10-05 16:55:19 -04:00
Peter Boyle 59b9d0e030 coalesceRead the blockSum 2023-10-05 16:54:48 -04:00
Peter Boyle b82eee4733 Hermitian dealing with 2023-10-05 16:54:14 -04:00
Peter Boyle 6a87487544 Running on Frontier, fix RNG big volume y2k, affecting 5D RNG 2023-10-05 16:50:59 -04:00
Peter Boyle fcf5023845 Running on Frontier 2023-10-05 16:50:59 -04:00
Peter Boyle c8adad6d8b First runs on Summit. PopulateAdag needs work 2023-10-05 16:50:54 -04:00
Peter Boyle 737d3ffb98 ADEF1 and 1 hop projection 2023-10-03 14:22:18 -04:00
Peter Boyle b01e67bab1 coalescedReadGeneralPermute now working 2023-10-02 17:46:57 -04:00
Peter Boyle 8a70314f54 Merge branch 'develop' into feature/scidac-wp1 2023-10-02 17:24:55 -04:00
Peter Boyle afc316f501 Rename headers 2023-10-02 16:25:11 -04:00
Peter Boyle f14bfd5c1b Relocate sub includes 2023-10-02 16:23:38 -04:00
Peter Boyle c5f1420dea Merge remote-tracking branch 'LupoA/develop' into LupoA-develop 2023-10-02 16:22:35 -04:00
Peter Boyle 36ae6e5aba Fastest GPU version. 
Need to work on the PaddedCell now to make much faster
 2023-09-29 18:26:51 -04:00
Peter Boyle 9db585cfeb Temporary commit while optimisation is carried out 2023-09-29 17:11:35 -04:00
Peter Boyle c564611ba7 Annoying hack that is useful to preserve for profiling 2023-09-29 17:11:12 -04:00
Peter Boyle e187bcb85c Updating 2023-09-29 17:10:17 -04:00
Peter Boyle be18ffe3b4 Further tuning and lanczos 2023-09-27 16:21:58 -04:00
Peter Boyle 0d63dce4e2 Timing info 2023-09-27 16:21:14 -04:00
Peter Boyle 26b30e1551 Flop count and projection to nearest neighbour (keeps redundant flops) 2023-09-27 16:20:11 -04:00
Peter Boyle 7fc58ac293 Verbose subspace init 2023-09-27 16:19:45 -04:00
Peter Boyle 3a86cce8c1 Compile 2023-09-27 16:19:18 -04:00
Peter Boyle 80359e0d49 Bland SYCL compile 2023-09-26 13:20:27 -07:00
Peter Boyle 3d437c5cc4 Making SYCL happy 2023-09-26 13:19:42 -07:00