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Author SHA1 Message Date
paboyle 4ab7dbfd57 Instantiate 2016-08-15 23:00:40 +01:00
paboyle 90e70790f3 Feature for z-Mobius prep 2016-08-15 22:31:29 +01:00
paboyle 5a68715be3 Richards sweep test 2016-08-05 10:51:57 +01:00
paboyle 32bc7a6ab8 MPI back out of change that hangs 
AVX2 for clang, gcc needs the -mfma flag.
 2016-08-05 10:36:00 +01:00
paboyle 27f3ecc833 Merge branch 'feature/bugfix-ck-cj' into develop 2016-07-16 01:59:52 +01:00
paboyle f9e90eeb1f Sign error on the force for 4d fields fixed 2016-07-16 01:52:44 +01:00
paboyle fad5c675eb sign error on the 4d gparity force 2016-07-16 01:51:56 +01:00
paboyle 4908b77d46 Fixed conflicts. PLEASE avoid making wholesale cosmetic only changes, this created 
a HUGE amount of difficult to resolve and understand conflicts .

Wholesale formatting, reordering functions etc... in a central file like Tensor_class
or Grid_vector_types while others are also editing without making substantial functionality
changes creates pain.
 2016-07-15 20:59:07 +01:00
paboyle f4dd5062d7 Merge branch 'develop' of https://github.com/paboyle/Grid into develop 2016-07-15 19:26:06 +01:00
paboyle da34d75841 Merge branch 'feature/Ls-vectorised-actions' into develop 2016-07-15 19:09:47 +01:00
paboyle 980ff18956 Solving the instantiation no compile issue 2016-07-15 17:19:44 +01:00
paboyle 1a6c7204ac Disable instantiation; Use cache version instead 2016-07-15 00:34:39 +01:00
paboyle 49310fbab3 Done with red black change over 2016-07-15 00:08:43 +01:00
paboyle 6049d5ac47 Update 2016-07-15 00:08:32 +01:00
paboyle 35d0d35238 Updated file list 2016-07-15 00:02:53 +01:00
paboyle c0e878705e Updated file list 2016-07-15 00:02:39 +01:00
paboyle 5c0c8efb9e Updated file list 2016-07-15 00:02:11 +01:00
paboyle dfd714e1ef Multiple implementations for the 5d hopping terms, depending on cache friendly 
ops and/or the 5th direction being vectorised
All use 4d redblack.
 2016-07-15 00:00:09 +01:00
paboyle 79a8ca1a62 Rewrite for performance. Impl dependent instantiations give 
4d linalg impls of the 5d hopping terms (and inverse)
Cache friendly loop orderings of the above
Dense matrix stored and apply to the above

-- Switch to Ls vectorised, and use dense matrix approach for the MooeeInv
   and rotate/shift of the Mooee M5D routines.
 2016-07-14 23:58:15 +01:00
paboyle fb45eb2eb2 5d ls vec rename of impl class 2016-07-14 23:57:26 +01:00
paboyle a307274c96 Fermion impl rename for ls vectorised 5d approaches 2016-07-14 23:56:13 +01:00
paboyle 3f2c44a5fe Updating the class to 5d selection based on impl type 2016-07-14 23:55:26 +01:00
paboyle 48fb1cdc11 Update domain 5d vectorised impl type, move the type over to 4d redblack with 
the dense OO inverse
 2016-07-14 23:54:35 +01:00
paboyle 8a79e93cc2 Rename the 5d domain wall fermion vectorised Ls impl class 2016-07-14 23:53:00 +01:00
paboyle 3493b51879 Modest updates 2016-07-14 23:52:13 +01:00
paboyle de3e79d300 red black for Ls vectorised is 4d red black. Update accordingly now I've made this choice 2016-07-14 23:49:42 +01:00
paboyle dd62a61c5c Added broadcast and rotation of simd vectors 2016-07-14 23:49:00 +01:00
paboyle 8f47d0b5ab Rotation needed for hopping term in fifth dim with Ls vectorised fields 2016-07-14 23:45:36 +01:00
paboyle 42af132dab Fix for chris kellys request to peek poke on checkerboarded fields 2016-07-14 23:44:48 +01:00
paboyle 9db2c6525d updating benchmarks for red black 4d for Ls vectorised code 2016-07-14 23:44:02 +01:00
paboyle adbc7c1188 Adding files for multiple implementations (cache opt) and Ls vectorisation 
of the 5D cayley form chiral fermions for the 5d matrix. With Ls entirely
in the vector direction, s-hopping terms involve rotations.

The serial dependence of the LDU inversion for Mobius and 4d even odd
checkerboarding is removed by simply applying Ls^2 operations (vectorised
many ways) as a dense matrix operation.

This should give similar throughput but high flops (non-compulsory flops)
but enable use of the KNL cache friendly kernels throughout the code.

Ls is still constrained to be a multiple of Nsimd, which is as much as 8 for AVX512
with single precision.
 2016-07-14 22:59:21 +01:00
paboyle 62601bb649 Bug fix 2016-07-08 20:46:29 +01:00
paboyle ef97e32152 Adding persistent communicators 2016-07-08 17:16:08 +01:00
paboyle c667d9fdcc Trying to make compile clean on travis; seem to have a make -j 4 problem with fftw 2016-07-07 23:26:39 +01:00
paboyle 7dbb94bab2 Update 2016-07-07 22:51:37 +01:00
paboyle 236dcc820b typo fix 2016-07-07 22:46:11 +01:00
paboyle a42a441a6a Rename the reconfigure script to ./autogen.sh 2016-07-07 22:35:45 +01:00
paboyle a0676beeb1 Open up dependency on Eigen and FFTW 2016-07-07 22:31:07 +01:00
paboyle fc4a043663 Colors and banner clean up 2016-07-02 16:15:38 +01:00
paboyle 61ba50665e Merge branch 'hotfix/v0.5.1' into develop 2016-07-01 16:34:30 +01:00
paboyle bfe14000a9 Double compile fix 2016-07-01 16:33:51 +01:00
paboyle 1ceff48133 Merge branch 'release/v0.5.0' into develop 2016-06-30 15:15:59 -07:00
paboyle 680645f849 Merge branch 'release/v0.5.0' 2016-06-30 15:15:03 -07:00
paboyle 3fc6e03ad1 Version file 2016-06-30 14:44:09 -07:00
paboyle 2d6614f3a1 Merge branch 'feature/knl-cache-opt' into develop 2016-06-30 14:36:20 -07:00
paboyle 4e041b5103 Merge branch 'feature/knl-cache-opt' of https://github.com/paboyle/Grid into feature/knl-cache-opt 2016-06-30 14:36:08 -07:00
paboyle 712b9a3489 Asm only for avx512 2016-06-30 14:35:02 -07:00
paboyle bdaa5b1767 Updated to have perfect prefetching for the s-vectorised kernel with any cache blocking. 2016-06-30 14:35:02 -07:00
paboyle 8fcefc021a Improved the prefetching when using cache blocking codes 2016-06-30 14:35:02 -07:00
paboyle 1445189361 COntrol the prefetch strategy 2016-06-30 14:35:02 -07:00
paboyle 05c884a62a Prefetch change 2016-06-30 14:35:01 -07:00
paboyle a25bec87d9 Prefetch during save 2016-06-30 14:35:01 -07:00
paboyle 2d8bb4c594 Tweaks 2016-06-30 14:35:01 -07:00
paboyle 51cb2d4328 update file lists 2016-06-30 14:35:01 -07:00
paboyle 6d58cb2a68 Enable reordering of the loops in the assembler for cache friendly. 
This gets in the way of L2 prefetching however. Do next next link in stencil
prefetching.
 2016-06-30 14:35:01 -07:00
paboyle c8b35d960c Merge branch 'develop' of https://github.com/paboyle/Grid into feature/knl-cache-opt 2016-06-30 14:30:49 -07:00
paboyle 532f41dd61 Asm only for avx512 2016-06-30 14:00:34 -07:00
paboyle 661b0ab45d Updated to have perfect prefetching for the s-vectorised kernel with any cache blocking. 2016-06-30 13:07:42 -07:00
paboyle 4bc08ed995 Improved the prefetching when using cache blocking codes 2016-06-26 12:54:14 -07:00
paboyle b2933a0557 COntrol the prefetch strategy 2016-06-25 12:55:25 -07:00
paboyle db057cc276 Prefetch change 2016-06-25 12:54:50 -07:00
paboyle 22e88eaf54 Prefetch during save 2016-06-25 12:54:14 -07:00
paboyle 09fe3caebd Tweaks 2016-06-25 11:08:05 -07:00
paboyle 17a8f51a9b update file lists 2016-06-19 11:59:10 -07:00
paboyle 1b7f88dd00 Enable reordering of the loops in the assembler for cache friendly. 
This gets in the way of L2 prefetching however. Do next next link in stencil
prefetching.
 2016-06-19 11:45:58 -07:00
paboyle 87418e7df1 Slightly faster prefetching perf. 2016-06-13 02:32:52 -07:00
paboyle 55f65b81b5 Improvements to the assembler interface that let us move chunks of the 
site and s loop into the kernels. This will save on function call overhead and
guarantee L2 prefetching strategy is right since OMP can't distribute the
sub-chunks of work.
 2016-06-09 01:12:36 -07:00
paboyle 05acc22920 placeholder for non temporal loads optimisation 2016-06-07 13:18:21 -07:00
paboyle 8ac021de73 Added a test an fixed it for red black precon Ls innermost vectorised DWF 2016-06-07 13:16:56 -07:00
paboyle e503ef5590 Cleaned up 2016-06-07 00:11:36 +01:00
paboyle a7682b0060 Only instantiate the one routine to avoid duplicate symbol under g++5/MacOS 2016-06-06 23:48:21 +01:00
paboyle d4c9d71fc8 Merge branch 'master' of https://github.com/paboyle/Grid 2016-06-06 07:06:54 -07:00
paboyle 786ca52c43 Problems remain in the red black preconditioning of the Ls vectorisation 2016-06-06 07:05:51 -07:00
paboyle 53d06046b0 Compiling updates for KNL 2016-06-03 03:47:54 -07:00
paboyle 5d3a1a025d timers flag 2016-06-03 03:25:38 -07:00
paboyle 139cc5f1ae Large change with KNL preparation 2016-06-03 03:24:26 -07:00
paboyle 3a5b5c8bec Save an old tar of tree 2016-05-12 03:20:17 -07:00
paboyle fdbe071213 space added 2016-05-12 02:59:51 -07:00
paboyle ab89418658 Precision change going in; useful for mixed precision algorithms for example. 2016-05-11 15:18:47 +01:00
paboyle 28cd99882c Subslicing 2016-05-11 15:06:54 +01:00
paboyle aceaee774c ExtractSlice / InsertSlice for lower dimensional lattices where the lattice is not 
distributed in the orthogonal direction.
Useful for fermion 4d/5d etc..
 2016-05-11 14:12:02 +01:00
paboyle c23375cd65 Testing travis CI integration 2016-04-30 06:30:56 -07:00
paboyle a762a0d9ff Attempt at CIT testing 2016-04-30 06:29:41 -07:00
paboyle f7ca6ca889 Bernoulli reenabled -- using integral type for the discrete_distribution, but 
then casts in the fill
 2016-04-30 03:48:28 -07:00
paboyle ec4a9b7f6c The Bernoulli gives a no compile due to a static assertion that the type be integral 
in 4.7 random.h

Probably need to go through an Integer type, and then conver to real after the random draw
to make clean.
 2016-04-30 03:42:24 -07:00
paboyle 5341977948 IMCI fixes. Thought I had committed these. The "real" disambiguation 
between std::real and Grid::real shouldn't have been necessary and I don't
know why only the icpc v16.0 on babbage hits it.
May need a longer term rename of Grid::real or some careful EnableIf work.
 2016-04-30 03:34:16 -07:00
paboyle 1e554350ac The threaded coms didn't agree with GCC. Suprised, and looks like GCC bug. 2016-04-29 16:49:18 -07:00
paboyle c79ea0dcef Fixingn IMCI 2016-04-22 21:52:54 -07:00
paboyle e3f141f82f Fixed SSE compile with typecasts 2016-04-22 10:30:30 -07:00
paboyle a6dfa2386b GCC choked on intrinsics calls that ICPC did not 2016-04-22 06:33:41 -07:00
paboyle 8fd8bc25e9 simd 5th dim with rotation 2016-04-19 15:39:00 -07:00
paboyle ba427abde9 simd 5d 2016-04-19 15:38:39 -07:00
paboyle 9b6ab6db16 simd in 5th dimension support 2016-04-19 15:38:01 -07:00
paboyle 806a83d38b simd in fifth dim support for dwf 2016-04-19 15:36:19 -07:00
paboyle 7223753355 Rotate in a direction > 2 for simd_layout 2016-04-19 15:35:15 -07:00
paboyle b27bac4669 Updates for simd in one dir 2016-04-19 15:34:10 -07:00
paboyle c8a93d6a93 Cartesian changes to allow all simd in one direction 2016-04-19 15:18:12 -07:00
paboyle 04072a5e1f Rotate is a temporary hack. Would like to merge ALL 
permutes as rotates of length 2, and make any rotate active
over any subset of lane bits. This is hard, and requires general
permute; current intrinsics mean this is only really possible for specific
case by case encodings as presently performed. Intel could produce a general
permute.. would help. IBM did it in VMX.
 2016-04-19 15:15:34 -07:00
paboyle 574ea4f843 const safety 2016-04-19 15:15:11 -07:00
paboyle f2ae9682ff Remove some timing hacks 2016-04-19 15:14:32 -07:00